diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala
index 8267d07c4..f6592c3f0 100644
--- a/elaborator/src/rocketv/Frontend.scala
+++ b/elaborator/src/rocketv/Frontend.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter}
 
@@ -137,7 +137,7 @@ object Frontend extends SerializableModuleElaborator {
   implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] =
     ParserForClass[FrontendParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala
index cd959e375..1c4c23301 100644
--- a/elaborator/src/rocketv/ICache.scala
+++ b/elaborator/src/rocketv/ICache.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.rocketv
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{ICache, ICacheParameter}
 
@@ -42,7 +42,7 @@ object ICache extends SerializableModuleElaborator {
 
   implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/rocketv/RocketTile.scala b/elaborator/src/rocketv/RocketTile.scala
index 9aaa130e5..a5db504fc 100644
--- a/elaborator/src/rocketv/RocketTile.scala
+++ b/elaborator/src/rocketv/RocketTile.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter}
 
@@ -191,7 +191,7 @@ object RocketTile extends SerializableModuleElaborator {
   implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] =
     ParserForClass[RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/t1/T1.scala b/elaborator/src/t1/T1.scala
index 59bfe8ebe..ea86983c8 100644
--- a/elaborator/src/t1/T1.scala
+++ b/elaborator/src/t1/T1.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -59,7 +59,7 @@ object T1 extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/t1emu/TestBench.scala b/elaborator/src/t1emu/TestBench.scala
index 1963195b0..c463c028b 100644
--- a/elaborator/src/t1emu/TestBench.scala
+++ b/elaborator/src/t1emu/TestBench.scala
@@ -3,7 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1emu
 
 import chisel3.experimental.util.SerializableModuleElaborator
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -60,7 +60,7 @@ object TestBench extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/t1rocket/T1RocketTile.scala b/elaborator/src/t1rocket/T1RocketTile.scala
index c7e15e326..d05e8c4f9 100644
--- a/elaborator/src/t1rocket/T1RocketTile.scala
+++ b/elaborator/src/t1rocket/T1RocketTile.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -112,7 +112,7 @@ object T1RocketTile extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/elaborator/src/t1rocketemu/TestBench.scala b/elaborator/src/t1rocketemu/TestBench.scala
index 7e07e5a1b..b0006709e 100644
--- a/elaborator/src/t1rocketemu/TestBench.scala
+++ b/elaborator/src/t1rocketemu/TestBench.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
-import chisel3.stage.IncludeUtilMetadata
+import chisel3.stage.{IncludeUtilMetadata, UseSRAMBlackbox}
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -113,7 +113,7 @@ object TestBench extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
-  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+  override def additionalAnnotations = Seq(IncludeUtilMetadata, UseSRAMBlackbox)
 
   @main
   def config(@arg(name = "parameter") parameter: M) =
diff --git a/nix/t1/dependencies/_sources/generated.json b/nix/t1/dependencies/_sources/generated.json
index 18156f5d4..4388b27b3 100644
--- a/nix/t1/dependencies/_sources/generated.json
+++ b/nix/t1/dependencies/_sources/generated.json
@@ -41,7 +41,7 @@
     },
     "chisel": {
         "cargoLocks": null,
-        "date": "2024-12-07",
+        "date": "2024-12-08",
         "extract": null,
         "name": "chisel",
         "passthru": null,
@@ -53,11 +53,11 @@
             "name": null,
             "owner": "chipsalliance",
             "repo": "chisel",
-            "rev": "5871a65195c7ad96edb9c58dd94cddd942815dfb",
-            "sha256": "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=",
+            "rev": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f",
+            "sha256": "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=",
             "type": "github"
         },
-        "version": "5871a65195c7ad96edb9c58dd94cddd942815dfb"
+        "version": "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f"
     },
     "chisel-interface": {
         "cargoLocks": null,
diff --git a/nix/t1/dependencies/_sources/generated.nix b/nix/t1/dependencies/_sources/generated.nix
index 221ea4452..79d0bce15 100644
--- a/nix/t1/dependencies/_sources/generated.nix
+++ b/nix/t1/dependencies/_sources/generated.nix
@@ -27,15 +27,15 @@
   };
   chisel = {
     pname = "chisel";
-    version = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
+    version = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
     src = fetchFromGitHub {
       owner = "chipsalliance";
       repo = "chisel";
-      rev = "5871a65195c7ad96edb9c58dd94cddd942815dfb";
+      rev = "a6196ca5b4ed2e5487d8be4507cc96516b5b3c8f";
       fetchSubmodules = false;
-      sha256 = "sha256-0xh7Xg2vi+GmoTQHNFJPQ5MP7r1UDmiGcJUI45YE16A=";
+      sha256 = "sha256-s6y4jlTvh4q6mWXCGzxxUtFaekZ9BDT9FhrSqvtWnwE=";
     };
-    date = "2024-12-07";
+    date = "2024-12-08";
   };
   chisel-interface = {
     pname = "chisel-interface";
diff --git a/omreaderlib/src/T1OMReaderAPI.scala b/omreaderlib/src/T1OMReaderAPI.scala
index 0fc21210f..1bc1dcecb 100644
--- a/omreaderlib/src/T1OMReaderAPI.scala
+++ b/omreaderlib/src/T1OMReaderAPI.scala
@@ -12,6 +12,7 @@ object SRAM {
 /** The SRAM Module to be replaced. */
 case class SRAM(
   moduleName:      String,
+  fullPath:        String,
   depth:           Int,
   width:           Int,
   read:            Int,
@@ -52,7 +53,7 @@ object Path {
   implicit val rw:        ReadWriter[Instruction] = macroRW
   def parse(str: String): Path                    =
     str match {
-      case s"OMReferenceTarget:~${top}|${hier}>${local}" =>
+      case s"OMInstanceTarget:~${top}|${hier}>${local}" =>
         Path(
           top,
           hier
@@ -63,7 +64,7 @@ object Path {
             }),
           Some(local)
         )
-      case s"OMReferenceTarget:~${top}|${hier}"          =>
+      case s"OMInstanceTarget:~${top}|${hier}"          =>
         Path(
           top,
           hier
diff --git a/omreaderlib/src/t1/T1.scala b/omreaderlib/src/t1/T1.scala
index a2418f76d..a859f4afe 100644
--- a/omreaderlib/src/t1/T1.scala
+++ b/omreaderlib/src/t1/T1.scala
@@ -54,9 +54,10 @@ class T1(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
         .field("srams")
         .asInstanceOf[PanamaCIRCTOMEvaluatorValueList]
       srams.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]).map { sram =>
+        val hierarchy = Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString)
         SRAM(
-          moduleName =
-            Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module,
+          moduleName = hierarchy.module,
+          fullPath = hierarchy.path,
           depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
           width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
           read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
diff --git a/omreaderlib/src/t1rocketv/T1RocketTile.scala b/omreaderlib/src/t1rocketv/T1RocketTile.scala
index 5688e191c..30cd89649 100644
--- a/omreaderlib/src/t1rocketv/T1RocketTile.scala
+++ b/omreaderlib/src/t1rocketv/T1RocketTile.scala
@@ -59,9 +59,10 @@ class T1RocketTile(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
         .field("srams")
         .asInstanceOf[PanamaCIRCTOMEvaluatorValueList]
       srams.elements().map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject]).map { sram =>
+        val hierarchy = Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString)
         SRAM(
-          moduleName =
-            Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module,
+          moduleName = hierarchy.module,
+          fullPath = hierarchy.path,
           depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
           width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
           read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
@@ -92,10 +93,11 @@ class T1RocketTile(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
         .asInstanceOf[PanamaCIRCTOMEvaluatorValueList]
         .elements()
         .map(_.asInstanceOf[PanamaCIRCTOMEvaluatorValueObject])
-        .map(sram =>
+        .map(sram => {
+          val hierarchy = Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString)
           SRAM(
-            moduleName =
-              Path.parse(sram.field("hierarchy").asInstanceOf[PanamaCIRCTOMEvaluatorValuePath].toString).module,
+            moduleName = hierarchy.module,
+            fullPath = hierarchy.path,
             depth = sram.field("depth").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
             width = sram.field("width").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
             read = sram.field("read").asInstanceOf[PanamaCIRCTOMEvaluatorValuePrimitiveInteger].integer.toInt,
@@ -107,7 +109,7 @@ class T1RocketTile(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
               .integer
               .toInt
           )
-        )
+        })
     )
     .distinct