From 2555596078808a6c4909c27326f24d1ed1613396 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Sun, 20 Oct 2024 21:34:37 +0000 Subject: [PATCH 1/2] [deps] Bump T1 dependencies --- nix/t1/dependencies/_sources/generated.json | 8 ++++---- nix/t1/dependencies/_sources/generated.nix | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/nix/t1/dependencies/_sources/generated.json b/nix/t1/dependencies/_sources/generated.json index ddf8e4ed2..1ae7e5240 100644 --- a/nix/t1/dependencies/_sources/generated.json +++ b/nix/t1/dependencies/_sources/generated.json @@ -41,7 +41,7 @@ }, "chisel": { "cargoLocks": null, - "date": "2024-10-16", + "date": "2024-10-18", "extract": null, "name": "chisel", "passthru": null, @@ -53,11 +53,11 @@ "name": null, "owner": "chipsalliance", "repo": "chisel", - "rev": "d564445dbcd81c6ac3319ef9442db2d177ae124f", - "sha256": "sha256-V8CxQ5VIkk2c+7KlQIcQX6Qe2PbMZI7/q+5e4iDXajI=", + "rev": "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f", + "sha256": "sha256-+njdHbPH6MpP6uIEliLTRyanJhCIWhnA2meJl8q1rso=", "type": "github" }, - "version": "d564445dbcd81c6ac3319ef9442db2d177ae124f" + "version": "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f" }, "chisel-interface": { "cargoLocks": null, diff --git a/nix/t1/dependencies/_sources/generated.nix b/nix/t1/dependencies/_sources/generated.nix index aa411b29d..19ed76d11 100644 --- a/nix/t1/dependencies/_sources/generated.nix +++ b/nix/t1/dependencies/_sources/generated.nix @@ -27,15 +27,15 @@ }; chisel = { pname = "chisel"; - version = "d564445dbcd81c6ac3319ef9442db2d177ae124f"; + version = "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "chisel"; - rev = "d564445dbcd81c6ac3319ef9442db2d177ae124f"; + rev = "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f"; fetchSubmodules = false; - sha256 = "sha256-V8CxQ5VIkk2c+7KlQIcQX6Qe2PbMZI7/q+5e4iDXajI="; + sha256 = "sha256-+njdHbPH6MpP6uIEliLTRyanJhCIWhnA2meJl8q1rso="; }; - date = "2024-10-16"; + date = "2024-10-18"; }; chisel-interface = { pname = "chisel-interface"; From a08ba7d0f58ba7a35d4afa477ec2f20c5c3e9ce4 Mon Sep 17 00:00:00 2001 From: unlsycn Date: Mon, 21 Oct 2024 12:03:53 +0000 Subject: [PATCH 2/2] [build system] fix elaborators of modules containing SRAMDescription --- elaborator/src/rocketv/Frontend.scala | 3 +++ elaborator/src/rocketv/ICache.scala | 3 +++ elaborator/src/rocketv/RocketTile.scala | 3 +++ elaborator/src/t1/T1.scala | 3 +++ elaborator/src/t1emu/TestBench.scala | 3 +++ elaborator/src/t1rocket/T1RocketTile.scala | 3 +++ elaborator/src/t1rocketemu/TestBench.scala | 3 +++ 7 files changed, 21 insertions(+) diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala index b341bf08d..8267d07c4 100644 --- a/elaborator/src/rocketv/Frontend.scala +++ b/elaborator/src/rocketv/Frontend.scala @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter} @@ -136,6 +137,8 @@ object Frontend extends SerializableModuleElaborator { implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] = ParserForClass[FrontendParameterMain] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala index 2edcc6c8d..cd959e375 100644 --- a/elaborator/src/rocketv/ICache.scala +++ b/elaborator/src/rocketv/ICache.scala @@ -3,6 +3,7 @@ package org.chipsalliance.t1.elaborator.rocketv import chisel3.experimental.util.SerializableModuleElaborator +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.rocketv.{ICache, ICacheParameter} @@ -41,6 +42,8 @@ object ICache extends SerializableModuleElaborator { implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/rocketv/RocketTile.scala b/elaborator/src/rocketv/RocketTile.scala index 390c5febe..9aaa130e5 100644 --- a/elaborator/src/rocketv/RocketTile.scala +++ b/elaborator/src/rocketv/RocketTile.scala @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter} @@ -190,6 +191,8 @@ object RocketTile extends SerializableModuleElaborator { implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] = ParserForClass[RocketTileParameterMain] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/t1/T1.scala b/elaborator/src/t1/T1.scala index dad8f2633..59bfe8ebe 100644 --- a/elaborator/src/t1/T1.scala +++ b/elaborator/src/t1/T1.scala @@ -3,6 +3,7 @@ package org.chipsalliance.t1.elaborator.t1 import chisel3.experimental.util.SerializableModuleElaborator +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.t1.rtl.vrf.RamType import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} @@ -58,6 +59,8 @@ object T1 extends SerializableModuleElaborator { implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/t1emu/TestBench.scala b/elaborator/src/t1emu/TestBench.scala index cc239559e..1963195b0 100644 --- a/elaborator/src/t1emu/TestBench.scala +++ b/elaborator/src/t1emu/TestBench.scala @@ -3,6 +3,7 @@ package org.chipsalliance.t1.elaborator.t1emu import chisel3.experimental.util.SerializableModuleElaborator +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.t1.rtl.vrf.RamType import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} @@ -59,6 +60,8 @@ object TestBench extends SerializableModuleElaborator { implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/t1rocket/T1RocketTile.scala b/elaborator/src/t1rocket/T1RocketTile.scala index fb7032dcc..c7e15e326 100644 --- a/elaborator/src/t1rocket/T1RocketTile.scala +++ b/elaborator/src/t1rocket/T1RocketTile.scala @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.t1.rtl.VFUInstantiateParameter import org.chipsalliance.t1.rtl.vrf.RamType @@ -111,6 +112,8 @@ object T1RocketTile extends SerializableModuleElaborator { implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] = ParserForClass[T1RocketTileParameterMain] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert)) diff --git a/elaborator/src/t1rocketemu/TestBench.scala b/elaborator/src/t1rocketemu/TestBench.scala index 46072ff26..7e07e5a1b 100644 --- a/elaborator/src/t1rocketemu/TestBench.scala +++ b/elaborator/src/t1rocketemu/TestBench.scala @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu import chisel3.experimental.util.SerializableModuleElaborator import chisel3.util.BitPat import chisel3.util.experimental.BitSet +import chisel3.stage.IncludeUtilMetadata import mainargs._ import org.chipsalliance.t1.rtl.VFUInstantiateParameter import org.chipsalliance.t1.rtl.vrf.RamType @@ -112,6 +113,8 @@ object TestBench extends SerializableModuleElaborator { implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] = ParserForClass[T1RocketTileParameterMain] + override def additionalAnnotations = Seq(IncludeUtilMetadata) + @main def config(@arg(name = "parameter") parameter: M) = os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))