Refactor t1's difftest organization

.github/workflows/lint.yml

@@ -53,11 +53,6 @@ jobs:
           warnOnFileChanged "* Cargo format fail, please run 'cd difftest; cargo -- format'"
           popd
 
-          pushd t1rocketemu
-          nix shell '.#cargo' '.#rustfmt' -c cargo fmt
-          warnOnFileChanged "* Cargo format fail, please run 'cd t1rocketemu; cargo fmt'"
-          popd
-
           # Disable for now
           # if nix run '.#ripgrep' -- '\p{Script=Han}' t1 > zh-hans.txt; then
           #   RET=1

README.md

@@ -8,7 +8,7 @@ T1 supports standard `Zve32f` and `Zve32x`, and `VLEN`/`DLEN` can be increased u
 
 T1 ships important vector machine features, e.g., lanes, chaining, and large LSU outstanding by default, but it can also be a general platform for MMIO DSA(Domain-Specific-Accelerators).
 
-T1 is designed with [Chisel](https://github.com/chipsalliance/chisel) and releasing `IPEmulator` to users.
+T1 is designed with [Chisel](https://github.com/chipsalliance/chisel) and releasing `T1Emulator` to users.
 
 T1 uses a forked version of the Rocket Core as the scalar part of T1. But we don't officially support it for now; it can be replaced by any other RISC-V Scalar CPU.
 
@@ -58,11 +58,11 @@ For tuning the ideal vector machines, follow these performance-tuning methodolog
 - Matching bandwidth for VRF, VFU, and LSU.
 - Based on your workload, determine the required VLEN as it dictates the VRF memory area.
 - Choose the memory type for the VRF, which will determine the chip frequency.
-- Run the IPEmulator and PnR for your workloads to tune micro-architecture.
+- Run the T1Emulator and PnR for your workloads to tune micro-architecture.
 
 ## Development Guide
 
-We have a IP emulator under the directory `./ipemu`. [Spike](https://github.com/riscv/riscv-isa-sim) is used as the reference scalar core, integrated with the verilated vector IP. Under the online differential-test strategy, the emulator compares the load/store and VRF writes between Spike and T1 to verify T1’s correctness.
+We have a IP emulator under the directory `./t1emu`. [Spike](https://github.com/riscv/riscv-isa-sim) is used as the reference scalar core, integrated with the verilated vector IP. Under the online differential-test strategy, the emulator compares the load/store and VRF writes between Spike and T1 to verify T1’s correctness.
 
 ### Docker images
 
@@ -248,7 +248,7 @@ $ mill -i elaborator  # build and run elaborator
 #### Developing DPI
 ```shell
 $ nix develop .#t1.<config-name>.ip.vcs-dpi-lib  # replace <config-name> with your configuration name
-$ cd ipemu/csrc
+$ cd t1emu/csrc
 $ cargo build --feature dpicommon/vcs
 ```
 

build.sc

@@ -137,9 +137,9 @@ trait T1Rocket extends millbuild.common.T1RocketModule with ScalafmtModule {
   def chiselIvy       = None
 }
 
-object ipemu extends IPEmulator
+object t1emu extends T1Emulator
 
-trait IPEmulator extends millbuild.common.IPEmulatorModule {
+trait T1Emulator extends millbuild.common.T1EmulatorModule {
   def scalaVersion = T(v.scala)
 
   def t1Module = t1
@@ -197,7 +197,7 @@ trait Elaborator extends millbuild.common.ElaboratorModule {
 
   def generators = Seq(
     t1,
-    ipemu,
+    t1emu,
     rocketv,
     rocketemu,
     t1rocket,
@@ -256,7 +256,7 @@ trait OMReader extends millbuild.common.OMReaderModule {
   */
 object t1package extends ScalaModule {
   def scalaVersion = T(v.scala)
-  def moduleDeps   = super.moduleDeps ++ Seq(t1, ipemu, panamaconverter, omreaderlib)
+  def moduleDeps   = super.moduleDeps ++ Seq(t1, t1emu, panamaconverter, omreaderlib)
   override def sourceJar: T[PathRef] = T(
     Jvm.createJar(
       T.traverse(transitiveModuleDeps)(dep => T.sequence(Seq(dep.allSources, dep.resources, dep.compileResources)))()

common.sc

@@ -104,7 +104,7 @@ trait EmuHelperModule
   extends ScalaModule
     with HasChisel
 
-trait IPEmulatorModule
+trait T1EmulatorModule
   extends ScalaModule
     with HasChisel {
   def t1Module: ScalaModule

difftest/Cargo.toml

@@ -1,9 +1,9 @@
 [workspace]
 resolver = "2"
 members = [
-    "test_common",
     "spike_rs",
-    "offline",
+    "offline_t1",
+    "offline_t1rocket",
     "dpi_t1",
     "dpi_t1rocket",
     "dpi_common",

difftest/default.nix

@@ -6,32 +6,36 @@
 }:
 
 { outputName
-, emuType
-, buildType
+, emuType ? ""
+, moduleType
 , enableTrace ? false
 }:
 
-assert lib.assertMsg (lib.elem emuType [ "verilator" "vcs" ]) "emuType is either 'vcs' nor 'verilator'";
-assert lib.assertMsg (lib.elem buildType [ "t1" "t1rocket" ]) "emuType is either 't1' nor 't1rocket'";
+assert let
+  available = [ "dpi_t1" "dpi_t1rocket" "offline_t1" "offline_t1rocket" ];
+in
+lib.assertMsg (lib.elem moduleType available) "emuType is not in ${lib.concatStringsSep ", " available}";
+# if emuType is empty, then moduleType must be offline-*, or user should give valid emuType
+assert lib.assertMsg ((emuType == "" && lib.hasPrefix "offline" moduleType) || (lib.elem emuType [ "verilator" "vcs" ])) "emuType is either 'vcs' nor 'verilator'";
 
 rustPlatform.buildRustPackage {
   name = outputName;
   src = with lib.fileset; toSource {
     root = ./.;
     fileset = unions [
       ./spike_rs
-      ./offline
+      ./offline_t1
+      ./offline_t1rocket
       ./dpi_common
       ./dpi_t1
       ./dpi_t1rocket
-      ./test_common
       ./Cargo.lock
       ./Cargo.toml
     ];
   };
 
-  buildFeatures = [ "dpi_common/${emuType}" ] ++ lib.optionals enableTrace [ "dpi_common/trace" ];
-  buildAndTestSubdir = "./dpi_${buildType}";
+  buildFeatures = [ ] ++ lib.optionals (lib.hasPrefix "dpi" moduleType) [ "dpi_common/${emuType}" ] ++ lib.optionals enableTrace [ "dpi_common/trace" ];
+  buildAndTestSubdir = "./${moduleType}";
 
   env = {
     SPIKE_LIB_DIR = "${libspike}/lib";
@@ -45,8 +49,13 @@ rustPlatform.buildRustPackage {
     lockFile = ./Cargo.lock;
   };
 
+  postInstall = lib.optionalString (lib.hasPrefix "offline" moduleType) ''
+    exe=$(find $out/bin -type f -name 'offline_*')
+    ln -s "$exe" $out/bin/offline
+  '';
+
   passthru = {
-    dpiLibPath = "/lib/libdpi_${buildType}.a";
+    dpiLibPath = "/lib/libdpi_${moduleType}.a";
     inherit enableTrace;
   };
 }

difftest/dpi_t1/src/drive.rs

@@ -124,6 +124,7 @@ impl Driver {
         &SpikeArgs {
           elf_file: args.elf_file.clone(),
           log_file: args.log_file.clone(),
+          log_level: "info".to_string(),
           vlen: args.vlen,
           dlen: args.dlen,
           set: args.set.clone(),

difftest/offline/Cargo.toml → difftest/offline_t1/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "offline"
+name = "offline_t1"
 version = "0.1.0"
 edition = "2021"
 
@@ -15,5 +15,4 @@ num-bigint = { workspace = true }
 libloading = "0.8.1"
 xmas-elf = "0.9.1"
 
-common = { path = "../test_common" }
 spike_rs = { path = "../spike_rs" }

difftest/offline/src/difftest.rs → difftest/offline_t1/src/difftest.rs

@@ -1,30 +1,21 @@
-use common::spike_runner::SpikeRunner;
+use spike_rs::runner::*;
 use std::path::Path;
-use tracing::info;
-
-use common::rtl_config::RTLConfig;
-use common::CommonArgs;
 
 use crate::dut::Dut;
 use crate::json_events::*;
 
 pub struct Difftest {
   runner: SpikeRunner,
   dut: Dut,
-
-  #[allow(dead_code)]
-  config: RTLConfig,
 }
 
 impl Difftest {
-  pub fn new(args: CommonArgs) -> Self {
-    let config = RTLConfig { vlen: args.vlen, dlen: args.dlen };
+  pub fn new(args: SpikeArgs) -> Self {
     Self {
       runner: SpikeRunner::new(&args, true),
       dut: Dut::new(Path::new(
         &args.log_file.expect("difftest must be run with a log file"),
       )),
-      config,
     }
   }
 
@@ -39,9 +30,7 @@ impl Difftest {
         Ok(())
       }
       JsonEvents::SimulationStop { reason, cycle } => {
-        info!("simulation stopped at cycle {}, reason {}", cycle, reason);
-        self.runner.cycle = *cycle;
-        Ok(())
+        anyhow::bail!("stop: simulation stopped at cycle {cycle}, reason {reason}")
       }
       JsonEvents::Issue { idx, cycle } => {
         self.runner.cycle = *cycle;

difftest/offline/src/json_events.rs → difftest/offline_t1/src/json_events.rs

@@ -1,18 +1,9 @@
-use common::spike_runner::SpikeRunner;
 use num_bigint::BigUint;
 use serde::{Deserialize, Deserializer};
+use spike_rs::runner::SpikeRunner;
 use spike_rs::spike_event::LSU_IDX_DEFAULT;
 use tracing::{debug, info};
 
-#[derive(Deserialize, Debug, PartialEq, Clone)]
-pub enum Opcode {
-  PutFullData = 0,
-  PutPartialData = 1,
-  Get = 4,
-  // AccessAckData = 0,
-  // AccessAck = 0,
-}
-
 fn bigint_to_vec_u8<'de, D>(deserializer: D) -> Result<Vec<u8>, D::Error>
 where
   D: Deserializer<'de>,
@@ -338,7 +329,7 @@ impl JsonEventRunner for SpikeRunner {
       );
 
       // if instruction writes rd, it will retire in check_rd()
-      if count == se.vrf_access_record.retired_writes && !se.is_rd_written {
+      if count == se.vrf_access_record.retired_writes && !se.is_rd_written && !se.is_fd_written {
         should_retire = Some(issue_idx);
       }
       // if all writes are committed, retire the se

difftest/offline/src/main.rs → difftest/offline_t1/src/main.rs

@@ -5,12 +5,11 @@ mod json_events;
 use clap::Parser;
 use tracing::info;
 
-use common::spike_runner::SpikeRunner;
-use common::CommonArgs;
+use spike_rs::runner::*;
 
 use crate::difftest::Difftest;
 
-fn run_spike(args: &CommonArgs) -> anyhow::Result<()> {
+fn run_spike(args: &SpikeArgs) -> anyhow::Result<()> {
   let mut count: u64 = 0;
 
   let spike = SpikeRunner::new(args, true);
@@ -32,7 +31,7 @@ fn run_spike(args: &CommonArgs) -> anyhow::Result<()> {
 
 fn main() -> anyhow::Result<()> {
   // parse args
-  let args = CommonArgs::parse();
+  let args = SpikeArgs::parse();
 
   args.setup_logger()?;
 

t1rocketemu/offline/Cargo.toml → difftest/offline_t1rocket/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "offline"
+name = "offline_t1rocket"
 version = "0.1.0"
 edition = "2021"
 
@@ -15,5 +15,4 @@ num-bigint = { workspace = true }
 libloading = "0.8.1"
 xmas-elf = "0.9.1"
 
-common = { path = "../test_common" }
 spike_rs = { path = "../spike_rs" }