From c50cfcb42e7f4c68d564afc416ad7079bd7c97a3 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Tue, 27 Aug 2024 18:42:45 +0800 Subject: [PATCH 1/2] [rocketv] Try to separate the floating point decode, 'fp' represents the instruction that will enter FPU. --- rocketv/src/Decoder.scala | 5 +++-- rocketv/src/RocketCore.scala | 14 ++------------ 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/rocketv/src/Decoder.scala b/rocketv/src/Decoder.scala index d82122cf5..fd2dfa213 100644 --- a/rocketv/src/Decoder.scala +++ b/rocketv/src/Decoder.scala @@ -165,14 +165,15 @@ case class DecoderParameter( object fp extends BoolDecodeField[RocketDecodePattern] { override def name: String = "fp" - override def genTable(op: RocketDecodePattern): BitPat = op.instruction.instructionSet.name match { + override def genTable(op: RocketDecodePattern): BitPat = (op.instruction.instructionSet.name, op) match { // format: off - case s if Seq( + case (s, _) if Seq( "rv_d", "rv64_d", "rv_f", "rv64_f", "rv_q", "rv64_q", "rv_zfh", "rv64_zfh", "rv_d_zfh", "rv_q_zfh", ).contains(s) => y + case (_, p) if p.vectorReadFRegFile => y case _ => n // format: on } diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index 67e95ea1f..9a8fa3b56 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -1409,13 +1409,7 @@ class Rocket(val parameter: RocketParameter) csr.io.csrStall || csr.io.singleStep && (exRegValid || memRegValid || wbRegValid) || idCsrEn && csr.io.decode(0).fpCsr && !io.fpu.map(_.fcsr_rdy).getOrElse(false.B) || io.traceStall || !clockEnable || - Option - .when(usingFPU)( - (idDecodeOutput(parameter.decoderParameter.fp) || idDecodeOutput( - parameter.decoderParameter.vectorReadFRs1 - )) && idStallFpu - ) - .getOrElse(false.B) || + Option.when(usingFPU)(idDecodeOutput(parameter.decoderParameter.fp) && idStallFpu).getOrElse(false.B) || idDecodeOutput(parameter.decoderParameter.mem) && dcacheBlocked || // reduce activity during D$ misses Option .when(usingMulDiv)( @@ -1509,11 +1503,7 @@ class Rocket(val parameter: RocketParameter) io.fpu.foreach { fpu => fpuDecoder.get.io.instruction := idInstruction fpu.dec := fpuDecoder.get.io.output - fpu.valid := !ctrlKilled && ( - idDecodeOutput(parameter.decoderParameter.fp) || - // vector read frs1 - (fpu.dec.ren1 && idDecodeOutput(parameter.decoderParameter.vector)) - ) + fpu.valid := !ctrlKilled && idDecodeOutput(parameter.decoderParameter.fp) fpu.killx := ctrlKillx fpu.killm := killmCommon fpu.inst := idInstruction From 0c9730f3d3e4014e1696bcedeafdcd3db536a37f Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 5 Sep 2024 17:38:41 +0800 Subject: [PATCH 2/2] [rocketv] All vector floating-point operations use the dynamic rounding mode. --- rocketv/src/FPU.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/rocketv/src/FPU.scala b/rocketv/src/FPU.scala index e8e11979f..9f4d20407 100644 --- a/rocketv/src/FPU.scala +++ b/rocketv/src/FPU.scala @@ -379,10 +379,9 @@ class FPU(val parameter: FPUParameter) def isOneOf(x: UInt, s: Seq[UInt]): Bool = VecInit(s.map(x === _)).asUInt.orR // we don't currently support round-max-magnitude (rm=4) - io.core.illegal_rm := isOneOf(io.core.inst(14, 12), Seq(5.U, 6.U)) || io.core.inst( - 14, - 12 - ) === 7.U && io.core.fcsr_rm >= 5.U + io.core.illegal_rm := + (isOneOf(io.core.inst(14, 12), Seq(5.U, 6.U)) && io.core.inst(6, 0) =/= "b1010111".U) || + io.core.inst(14, 12) === 7.U && io.core.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight