diff --git a/.github/cases/blastoise/default.json b/.github/cases/blastoise/default.json
index 14a4b6fd1..8c2e502b9 100644
--- a/.github/cases/blastoise/default.json
+++ b/.github/cases/blastoise/default.json
@@ -13,7 +13,7 @@
   "codegen.vaaddu_vv": 91859,
   "codegen.vaaddu_vx": 253663,
   "codegen.vadc_vim": 24447,
-  "codegen.vadc_vvm": 11643,
+  "codegen.vadc_vvm": 11644,
   "codegen.vadc_vxm": 31030,
   "codegen.vadd_vi": 49930,
   "codegen.vadd_vv": 23267,
@@ -27,137 +27,137 @@
   "codegen.vasubu_vx": 253663,
   "codegen.vcompress_vm": 22146,
   "codegen.vcpop_m": 1845,
-  "codegen.vdiv_vv": 32539,
+  "codegen.vdiv_vv": 32540,
   "codegen.vdiv_vx": 195383,
-  "codegen.vdivu_vv": 32635,
+  "codegen.vdivu_vv": 32636,
   "codegen.vdivu_vx": 203376,
   "codegen.vfirst_m": 1757,
-  "codegen.vid_v": 16010,
+  "codegen.vid_v": 16011,
   "codegen.viota_m": 43475,
-  "codegen.vl1re16_v": 691,
-  "codegen.vl1re32_v": 691,
-  "codegen.vl1re8_v": 691,
-  "codegen.vl2re16_v": 725,
-  "codegen.vl2re32_v": 725,
-  "codegen.vl2re8_v": 725,
-  "codegen.vl4re16_v": 793,
-  "codegen.vl4re32_v": 793,
-  "codegen.vl4re8_v": 793,
-  "codegen.vl8re16_v": 932,
-  "codegen.vl8re32_v": 929,
-  "codegen.vl8re8_v": 929,
+  "codegen.vl1re16_v": 692,
+  "codegen.vl1re32_v": 692,
+  "codegen.vl1re8_v": 692,
+  "codegen.vl2re16_v": 726,
+  "codegen.vl2re32_v": 726,
+  "codegen.vl2re8_v": 726,
+  "codegen.vl4re16_v": 794,
+  "codegen.vl4re32_v": 794,
+  "codegen.vl4re8_v": 794,
+  "codegen.vl8re16_v": 933,
+  "codegen.vl8re32_v": 930,
+  "codegen.vl8re8_v": 930,
   "codegen.vle16_v": 5080,
   "codegen.vle16ff_v": 9387,
   "codegen.vle32_v": 4308,
   "codegen.vle32ff_v": 6276,
   "codegen.vle8_v": 5838,
-  "codegen.vle8ff_v": 15712,
+  "codegen.vle8ff_v": 15713,
   "codegen.vlm_v": 732,
-  "codegen.vloxei16_v": 29312,
+  "codegen.vloxei16_v": 29313,
   "codegen.vloxei32_v": 17670,
   "codegen.vloxei8_v": 41487,
   "codegen.vloxseg2ei16_v": 27608,
-  "codegen.vloxseg2ei32_v": 17328,
+  "codegen.vloxseg2ei32_v": 17329,
   "codegen.vloxseg2ei8_v": 34145,
-  "codegen.vloxseg3ei16_v": 19259,
-  "codegen.vloxseg3ei32_v": 13217,
-  "codegen.vloxseg3ei8_v": 25302,
-  "codegen.vloxseg4ei16_v": 21528,
-  "codegen.vloxseg4ei32_v": 14212,
-  "codegen.vloxseg4ei8_v": 29226,
-  "codegen.vloxseg5ei16_v": 12343,
-  "codegen.vloxseg5ei32_v": 7567,
-  "codegen.vloxseg5ei8_v": 18277,
-  "codegen.vloxseg6ei16_v": 13186,
-  "codegen.vloxseg6ei32_v": 7967,
-  "codegen.vloxseg6ei8_v": 20081,
-  "codegen.vloxseg7ei16_v": 14029,
-  "codegen.vloxseg7ei32_v": 8367,
-  "codegen.vloxseg7ei8_v": 21885,
-  "codegen.vloxseg8ei16_v": 14872,
-  "codegen.vloxseg8ei32_v": 8767,
-  "codegen.vloxseg8ei8_v": 23689,
+  "codegen.vloxseg3ei16_v": 19260,
+  "codegen.vloxseg3ei32_v": 13218,
+  "codegen.vloxseg3ei8_v": 25303,
+  "codegen.vloxseg4ei16_v": 21529,
+  "codegen.vloxseg4ei32_v": 14213,
+  "codegen.vloxseg4ei8_v": 29227,
+  "codegen.vloxseg5ei16_v": 12344,
+  "codegen.vloxseg5ei32_v": 7568,
+  "codegen.vloxseg5ei8_v": 18278,
+  "codegen.vloxseg6ei16_v": 13187,
+  "codegen.vloxseg6ei32_v": 7968,
+  "codegen.vloxseg6ei8_v": 20082,
+  "codegen.vloxseg7ei16_v": 14030,
+  "codegen.vloxseg7ei32_v": 8368,
+  "codegen.vloxseg7ei8_v": 21886,
+  "codegen.vloxseg8ei16_v": 14873,
+  "codegen.vloxseg8ei32_v": 8768,
+  "codegen.vloxseg8ei8_v": 23690,
   "codegen.vlse16_v": 41373,
   "codegen.vlse32_v": 26608,
-  "codegen.vlse8_v": 72148,
+  "codegen.vlse8_v": 72149,
   "codegen.vlseg2e16_v": 4557,
   "codegen.vlseg2e32_v": 3682,
   "codegen.vlseg2e8_v": 5402,
-  "codegen.vlseg3e16_v": 3850,
+  "codegen.vlseg3e16_v": 3851,
   "codegen.vlseg3e32_v": 2806,
-  "codegen.vlseg3e8_v": 4896,
+  "codegen.vlseg3e8_v": 4897,
   "codegen.vlseg4e16_v": 3978,
   "codegen.vlseg4e32_v": 2896,
   "codegen.vlseg4e8_v": 5050,
-  "codegen.vlseg5e16_v": 3142,
+  "codegen.vlseg5e16_v": 3143,
   "codegen.vlseg5e32_v": 1821,
-  "codegen.vlseg5e8_v": 4554,
+  "codegen.vlseg5e8_v": 4555,
   "codegen.vlseg6e16_v": 3204,
   "codegen.vlseg6e32_v": 1863,
-  "codegen.vlseg6e8_v": 4644,
+  "codegen.vlseg6e8_v": 4645,
   "codegen.vlseg7e16_v": 3266,
   "codegen.vlseg7e32_v": 1905,
-  "codegen.vlseg7e8_v": 4750,
-  "codegen.vlseg8e16_v": 3324,
-  "codegen.vlseg8e32_v": 1943,
-  "codegen.vlseg8e8_v": 4840,
+  "codegen.vlseg7e8_v": 4751,
+  "codegen.vlseg8e16_v": 3325,
+  "codegen.vlseg8e32_v": 1944,
+  "codegen.vlseg8e8_v": 4841,
   "codegen.vlsseg2e16_v": 36703,
-  "codegen.vlsseg2e32_v": 21878,
-  "codegen.vlsseg2e8_v": 63758,
+  "codegen.vlsseg2e32_v": 21879,
+  "codegen.vlsseg2e8_v": 63759,
   "codegen.vlsseg3e16_v": 27053,
-  "codegen.vlsseg3e32_v": 14618,
-  "codegen.vlsseg3e8_v": 50953,
+  "codegen.vlsseg3e32_v": 14619,
+  "codegen.vlsseg3e8_v": 50954,
   "codegen.vlsseg4e16_v": 31308,
-  "codegen.vlsseg4e32_v": 16188,
-  "codegen.vlsseg4e8_v": 61548,
-  "codegen.vlsseg5e16_v": 19338,
-  "codegen.vlsseg5e32_v": 9043,
-  "codegen.vlsseg5e8_v": 43788,
-  "codegen.vlsseg6e16_v": 20953,
-  "codegen.vlsseg6e32_v": 9703,
-  "codegen.vlsseg6e8_v": 49183,
-  "codegen.vlsseg7e16_v": 22568,
-  "codegen.vlsseg7e32_v": 10363,
-  "codegen.vlsseg7e8_v": 54578,
-  "codegen.vlsseg8e16_v": 24183,
-  "codegen.vlsseg8e32_v": 11023,
-  "codegen.vlsseg8e8_v": 59973,
-  "codegen.vluxei16_v": 29312,
+  "codegen.vlsseg4e32_v": 16189,
+  "codegen.vlsseg4e8_v": 61549,
+  "codegen.vlsseg5e16_v": 19339,
+  "codegen.vlsseg5e32_v": 9044,
+  "codegen.vlsseg5e8_v": 43789,
+  "codegen.vlsseg6e16_v": 20954,
+  "codegen.vlsseg6e32_v": 9704,
+  "codegen.vlsseg6e8_v": 49184,
+  "codegen.vlsseg7e16_v": 22569,
+  "codegen.vlsseg7e32_v": 10364,
+  "codegen.vlsseg7e8_v": 54579,
+  "codegen.vlsseg8e16_v": 24184,
+  "codegen.vlsseg8e32_v": 11024,
+  "codegen.vlsseg8e8_v": 59974,
+  "codegen.vluxei16_v": 29313,
   "codegen.vluxei32_v": 17670,
   "codegen.vluxei8_v": 41487,
   "codegen.vluxseg2ei16_v": 27608,
-  "codegen.vluxseg2ei32_v": 17328,
+  "codegen.vluxseg2ei32_v": 17329,
   "codegen.vluxseg2ei8_v": 34145,
-  "codegen.vluxseg3ei16_v": 19259,
-  "codegen.vluxseg3ei32_v": 13217,
-  "codegen.vluxseg3ei8_v": 25302,
-  "codegen.vluxseg4ei16_v": 21528,
-  "codegen.vluxseg4ei32_v": 14212,
-  "codegen.vluxseg4ei8_v": 29226,
-  "codegen.vluxseg5ei16_v": 12343,
-  "codegen.vluxseg5ei32_v": 7567,
-  "codegen.vluxseg5ei8_v": 18277,
-  "codegen.vluxseg6ei16_v": 13186,
-  "codegen.vluxseg6ei32_v": 7967,
-  "codegen.vluxseg6ei8_v": 20081,
-  "codegen.vluxseg7ei16_v": 14029,
-  "codegen.vluxseg7ei32_v": 8367,
-  "codegen.vluxseg7ei8_v": 21885,
-  "codegen.vluxseg8ei16_v": 14872,
-  "codegen.vluxseg8ei32_v": 8767,
-  "codegen.vluxseg8ei8_v": 23689,
-  "codegen.vmacc_vv": 24077,
+  "codegen.vluxseg3ei16_v": 19260,
+  "codegen.vluxseg3ei32_v": 13218,
+  "codegen.vluxseg3ei8_v": 25303,
+  "codegen.vluxseg4ei16_v": 21529,
+  "codegen.vluxseg4ei32_v": 14213,
+  "codegen.vluxseg4ei8_v": 29227,
+  "codegen.vluxseg5ei16_v": 12344,
+  "codegen.vluxseg5ei32_v": 7568,
+  "codegen.vluxseg5ei8_v": 18278,
+  "codegen.vluxseg6ei16_v": 13187,
+  "codegen.vluxseg6ei32_v": 7968,
+  "codegen.vluxseg6ei8_v": 20082,
+  "codegen.vluxseg7ei16_v": 14030,
+  "codegen.vluxseg7ei32_v": 8368,
+  "codegen.vluxseg7ei8_v": 21886,
+  "codegen.vluxseg8ei16_v": 14873,
+  "codegen.vluxseg8ei32_v": 8768,
+  "codegen.vluxseg8ei8_v": 23690,
+  "codegen.vmacc_vv": 24078,
   "codegen.vmacc_vx": 76097,
   "codegen.vmadc_vi": 36009,
   "codegen.vmadc_vim": 37359,
-  "codegen.vmadc_vv": 10944,
-  "codegen.vmadc_vvm": 12342,
+  "codegen.vmadc_vv": 10945,
+  "codegen.vmadc_vvm": 12343,
   "codegen.vmadc_vx": 49557,
   "codegen.vmadc_vxm": 50907,
-  "codegen.vmadd_vv": 24077,
+  "codegen.vmadd_vv": 24078,
   "codegen.vmadd_vx": 76097,
-  "codegen.vmand_mm": 9982,
-  "codegen.vmandn_mm": 9982,
+  "codegen.vmand_mm": 9983,
+  "codegen.vmandn_mm": 9983,
   "codegen.vmax_vv": 23267,
   "codegen.vmax_vx": 63718,
   "codegen.vmaxu_vv": 23267,
@@ -169,15 +169,15 @@
   "codegen.vmin_vx": 63718,
   "codegen.vminu_vv": 23267,
   "codegen.vminu_vx": 63718,
-  "codegen.vmnand_mm": 9982,
-  "codegen.vmnor_mm": 9982,
-  "codegen.vmor_mm": 9982,
-  "codegen.vmorn_mm": 9982,
-  "codegen.vmsbc_vv": 10944,
-  "codegen.vmsbc_vvm": 12294,
+  "codegen.vmnand_mm": 9983,
+  "codegen.vmnor_mm": 9983,
+  "codegen.vmor_mm": 9983,
+  "codegen.vmorn_mm": 9983,
+  "codegen.vmsbc_vv": 10945,
+  "codegen.vmsbc_vvm": 12295,
   "codegen.vmsbc_vx": 49557,
   "codegen.vmsbc_vxm": 50907,
-  "codegen.vmsbf_m": 1605,
+  "codegen.vmsbf_m": 1606,
   "codegen.vmseq_vi": 79796,
   "codegen.vmseq_vv": 24968,
   "codegen.vmseq_vx": 109241,
@@ -187,7 +187,7 @@
   "codegen.vmsgtu_vi": 79796,
   "codegen.vmsgtu_vv": 24848,
   "codegen.vmsgtu_vx": 109241,
-  "codegen.vmsif_m": 1605,
+  "codegen.vmsif_m": 1606,
   "codegen.vmsle_vi": 79796,
   "codegen.vmsle_vv": 24968,
   "codegen.vmsle_vx": 109241,
@@ -201,14 +201,14 @@
   "codegen.vmsne_vi": 79796,
   "codegen.vmsne_vv": 24968,
   "codegen.vmsne_vx": 109241,
-  "codegen.vmsof_m": 1605,
-  "codegen.vmul_vv": 23482,
+  "codegen.vmsof_m": 1606,
+  "codegen.vmul_vv": 23483,
   "codegen.vmul_vx": 85696,
-  "codegen.vmulh_vv": 23482,
+  "codegen.vmulh_vv": 23483,
   "codegen.vmulh_vx": 85696,
-  "codegen.vmulhsu_vv": 23482,
+  "codegen.vmulhsu_vv": 23483,
   "codegen.vmulhsu_vx": 85696,
-  "codegen.vmulhu_vv": 23482,
+  "codegen.vmulhu_vv": 23483,
   "codegen.vmulhu_vx": 85696,
   "codegen.vmv_s_x": 1300,
   "codegen.vmv_v_i": 17795,
@@ -217,43 +217,43 @@
   "codegen.vmv_x_s": 1780,
   "codegen.vmv1r_v": 1699,
   "codegen.vmv2r_v": 1805,
-  "codegen.vmv4r_v": 2044,
-  "codegen.vmv8r_v": 2525,
-  "codegen.vmxnor_mm": 9982,
-  "codegen.vmxor_mm": 9982,
+  "codegen.vmv4r_v": 2045,
+  "codegen.vmv8r_v": 2526,
+  "codegen.vmxnor_mm": 9983,
+  "codegen.vmxor_mm": 9983,
   "codegen.vnclip_wi": 153531,
-  "codegen.vnclip_wv": 60647,
+  "codegen.vnclip_wv": 60648,
   "codegen.vnclip_wx": 198763,
   "codegen.vnclipu_wi": 153531,
-  "codegen.vnclipu_wv": 60647,
+  "codegen.vnclipu_wv": 60648,
   "codegen.vnclipu_wx": 198763,
-  "codegen.vnmsac_vv": 24077,
+  "codegen.vnmsac_vv": 24078,
   "codegen.vnmsac_vx": 76097,
-  "codegen.vnmsub_vv": 24077,
+  "codegen.vnmsub_vv": 24078,
   "codegen.vnmsub_vx": 76097,
   "codegen.vnsra_wi": 38685,
-  "codegen.vnsra_wv": 15464,
+  "codegen.vnsra_wv": 15465,
   "codegen.vnsra_wx": 49993,
   "codegen.vnsrl_wi": 38685,
-  "codegen.vnsrl_wv": 15464,
+  "codegen.vnsrl_wv": 15465,
   "codegen.vnsrl_wx": 49993,
   "codegen.vor_vi": 49901,
   "codegen.vor_vv": 23267,
   "codegen.vor_vx": 63692,
-  "codegen.vredand_vs": 28935,
-  "codegen.vredmax_vs": 28935,
-  "codegen.vredmaxu_vs": 28935,
-  "codegen.vredmin_vs": 28935,
-  "codegen.vredminu_vs": 28935,
-  "codegen.vredor_vs": 28935,
-  "codegen.vredsum_vs": 28935,
-  "codegen.vredxor_vs": 28935,
-  "codegen.vrem_vv": 32539,
+  "codegen.vredand_vs": 28936,
+  "codegen.vredmax_vs": 28936,
+  "codegen.vredmaxu_vs": 28936,
+  "codegen.vredmin_vs": 28936,
+  "codegen.vredminu_vs": 28936,
+  "codegen.vredor_vs": 28936,
+  "codegen.vredsum_vs": 28936,
+  "codegen.vredxor_vs": 28936,
+  "codegen.vrem_vv": 32540,
   "codegen.vrem_vx": 195383,
-  "codegen.vremu_vv": 32635,
+  "codegen.vremu_vv": 32636,
   "codegen.vremu_vx": 203376,
   "codegen.vrgather_vi": 92271,
-  "codegen.vrgather_vv": 101644,
+  "codegen.vrgather_vv": 101645,
   "codegen.vrgather_vx": 100633,
   "codegen.vrgatherei16_vv": 74439,
   "codegen.vrsub_vi": 49930,
@@ -268,16 +268,16 @@
   "codegen.vsaddu_vi": 49930,
   "codegen.vsaddu_vv": 23267,
   "codegen.vsaddu_vx": 63718,
-  "codegen.vsbc_vvm": 11643,
+  "codegen.vsbc_vvm": 11644,
   "codegen.vsbc_vxm": 45634,
   "codegen.vse16_v": 3957,
   "codegen.vse32_v": 3347,
   "codegen.vse8_v": 4567,
-  "codegen.vsetivli": 412,
-  "codegen.vsetvl": 412,
-  "codegen.vsetvli": 412,
+  "codegen.vsetivli": 413,
+  "codegen.vsetvl": 413,
+  "codegen.vsetvli": 413,
   "codegen.vsext_vf2": 23156,
-  "codegen.vsext_vf4": 4184,
+  "codegen.vsext_vf4": 4185,
   "codegen.vslide1down_vx": 866459,
   "codegen.vslide1up_vx": 860747,
   "codegen.vslidedown_vi": 609497,
@@ -285,10 +285,10 @@
   "codegen.vslideup_vi": 605949,
   "codegen.vslideup_vx": 859915,
   "codegen.vsll_vi": 62724,
-  "codegen.vsll_vv": 25692,
+  "codegen.vsll_vv": 25693,
   "codegen.vsll_vx": 81160,
   "codegen.vsm_v": 671,
-  "codegen.vsmul_vv": 92719,
+  "codegen.vsmul_vv": 92720,
   "codegen.vsmul_vx": 258767,
   "codegen.vsoxei16_v": 27337,
   "codegen.vsoxei32_v": 16204,
@@ -315,40 +315,40 @@
   "codegen.vsoxseg8ei32_v": 8265,
   "codegen.vsoxseg8ei8_v": 23769,
   "codegen.vsra_vi": 62724,
-  "codegen.vsra_vv": 25692,
+  "codegen.vsra_vv": 25693,
   "codegen.vsra_vx": 81160,
   "codegen.vsrl_vi": 62724,
-  "codegen.vsrl_vv": 25692,
+  "codegen.vsrl_vv": 25693,
   "codegen.vsrl_vx": 81160,
   "codegen.vsse16_v": 49611,
   "codegen.vsse32_v": 35399,
   "codegen.vsse8_v": 77187,
-  "codegen.vsseg2e16_v": 3643,
-  "codegen.vsseg2e32_v": 2945,
-  "codegen.vsseg2e8_v": 4341,
+  "codegen.vsseg2e16_v": 3644,
+  "codegen.vsseg2e32_v": 2946,
+  "codegen.vsseg2e8_v": 4342,
   "codegen.vsseg3e16_v": 3105,
   "codegen.vsseg3e32_v": 2279,
   "codegen.vsseg3e8_v": 3931,
-  "codegen.vsseg4e16_v": 3281,
-  "codegen.vsseg4e32_v": 2407,
-  "codegen.vsseg4e8_v": 4155,
+  "codegen.vsseg4e16_v": 3282,
+  "codegen.vsseg4e32_v": 2408,
+  "codegen.vsseg4e8_v": 4156,
   "codegen.vsseg5e16_v": 2567,
   "codegen.vsseg5e32_v": 1485,
   "codegen.vsseg5e8_v": 3649,
-  "codegen.vsseg6e16_v": 2663,
-  "codegen.vsseg6e32_v": 1533,
-  "codegen.vsseg6e8_v": 3793,
+  "codegen.vsseg6e16_v": 2664,
+  "codegen.vsseg6e32_v": 1534,
+  "codegen.vsseg6e8_v": 3794,
   "codegen.vsseg7e16_v": 2759,
   "codegen.vsseg7e32_v": 1581,
   "codegen.vsseg7e8_v": 3937,
-  "codegen.vsseg8e16_v": 2855,
-  "codegen.vsseg8e32_v": 1629,
-  "codegen.vsseg8e8_v": 4081,
-  "codegen.vssra_vi": 249687,
-  "codegen.vssra_vv": 101559,
+  "codegen.vsseg8e16_v": 2856,
+  "codegen.vsseg8e32_v": 1630,
+  "codegen.vsseg8e8_v": 4082,
+  "codegen.vssra_vi": 249688,
+  "codegen.vssra_vv": 101560,
   "codegen.vssra_vx": 484543,
-  "codegen.vssrl_vi": 249687,
-  "codegen.vssrl_vv": 101559,
+  "codegen.vssrl_vi": 249688,
+  "codegen.vssrl_vv": 101560,
   "codegen.vssrl_vx": 484543,
   "codegen.vssseg2e16_v": 43771,
   "codegen.vssseg2e32_v": 29255,
@@ -403,40 +403,40 @@
   "codegen.vsuxseg8ei8_v": 23769,
   "codegen.vwadd_vv": 13853,
   "codegen.vwadd_vx": 39634,
-  "codegen.vwadd_wv": 15180,
+  "codegen.vwadd_wv": 15181,
   "codegen.vwadd_wx": 46485,
   "codegen.vwaddu_vv": 13853,
   "codegen.vwaddu_vx": 39634,
-  "codegen.vwaddu_wv": 15180,
+  "codegen.vwaddu_wv": 15181,
   "codegen.vwaddu_wx": 46485,
-  "codegen.vwmacc_vv": 14922,
+  "codegen.vwmacc_vv": 14923,
   "codegen.vwmacc_vx": 57321,
-  "codegen.vwmaccsu_vv": 14922,
+  "codegen.vwmaccsu_vv": 14923,
   "codegen.vwmaccsu_vx": 57321,
-  "codegen.vwmaccu_vv": 14922,
+  "codegen.vwmaccu_vv": 14923,
   "codegen.vwmaccu_vx": 57321,
   "codegen.vwmaccus_vx": 57321,
-  "codegen.vwmul_vv": 13997,
+  "codegen.vwmul_vv": 13998,
   "codegen.vwmul_vx": 53394,
-  "codegen.vwmulsu_vv": 13997,
+  "codegen.vwmulsu_vv": 13998,
   "codegen.vwmulsu_vx": 53394,
-  "codegen.vwmulu_vv": 13997,
+  "codegen.vwmulu_vv": 13998,
   "codegen.vwmulu_vx": 53394,
   "codegen.vwredsum_vs": 17203,
   "codegen.vwredsumu_vs": 17203,
   "codegen.vwsub_vv": 13853,
   "codegen.vwsub_vx": 39634,
-  "codegen.vwsub_wv": 15180,
+  "codegen.vwsub_wv": 15181,
   "codegen.vwsub_wx": 46485,
   "codegen.vwsubu_vv": 13853,
   "codegen.vwsubu_vx": 39634,
-  "codegen.vwsubu_wv": 15180,
+  "codegen.vwsubu_wv": 15181,
   "codegen.vwsubu_wx": 46485,
   "codegen.vxor_vi": 49901,
   "codegen.vxor_vv": 23267,
   "codegen.vxor_vx": 63692,
   "codegen.vzext_vf2": 23156,
-  "codegen.vzext_vf4": 4184,
+  "codegen.vzext_vf4": 4185,
   "codegen.vfadd_vv": 91907,
   "codegen.vfadd_vf": 322675,
   "codegen.vfsub_vv": 91907,
@@ -445,8 +445,8 @@
   "codegen.vfmul_vv": 91907,
   "codegen.vfmul_vf": 322675,
   "codegen.vfdiv_vv": 133524,
-  "codegen.vfdiv_vf": 668303,
-  "codegen.vfrdiv_vf": 668303,
+  "codegen.vfdiv_vf": 668304,
+  "codegen.vfrdiv_vf": 668304,
   "codegen.vfmacc_vv": 95267,
   "codegen.vfmacc_vf": 379027,
   "codegen.vfnmacc_vv": 95267,
@@ -463,7 +463,7 @@
   "codegen.vfmsub_vf": 379027,
   "codegen.vfnmsub_vv": 95267,
   "codegen.vfnmsub_vf": 379027,
-  "codegen.vfsqrt_v": 9891,
+  "codegen.vfsqrt_v": 9892,
   "codegen.vfrsqrt7_v": 6086,
   "codegen.vfrec7_v": 6107,
   "codegen.vfmin_vv": 91907,
@@ -477,14 +477,14 @@
   "codegen.vfsgnjx_vv": 91907,
   "codegen.vfsgnjx_vf": 276675,
   "codegen.vmfeq_vv": 99155,
-  "codegen.vmfeq_vf": 558627,
+  "codegen.vmfeq_vf": 558628,
   "codegen.vmfne_vv": 99155,
-  "codegen.vmfne_vf": 558627,
+  "codegen.vmfne_vf": 558628,
   "codegen.vmflt_vv": 99155,
-  "codegen.vmflt_vf": 558627,
-  "codegen.vmfgt_vf": 558627,
-  "codegen.vmfge_vf": 558627,
-  "codegen.vfclass_v": 6167,
+  "codegen.vmflt_vf": 558628,
+  "codegen.vmfgt_vf": 558628,
+  "codegen.vmfge_vf": 558628,
+  "codegen.vfclass_v": 6168,
   "codegen.vfmerge_vfm": 185579,
   "codegen.vfmv_v_f": 2177,
   "codegen.vfmv_f_s": 8035,
@@ -496,9 +496,9 @@
   "codegen.vfcvt_f_xu_v": 6077,
   "codegen.vfcvt_f_x_v": 6083,
   "codegen.vfredosum_vs": 160515,
-  "codegen.vfredusum_vs": 122275,
-  "codegen.vfredmax_vs": 122275,
-  "codegen.vfredmin_vs": 122275,
+  "codegen.vfredusum_vs": 122276,
+  "codegen.vfredmax_vs": 122276,
+  "codegen.vfredmin_vs": 122276,
   "rvv_bench.ascii_to_utf16": 1583663,
   "rvv_bench.ascii_to_utf32": 703954,
   "rvv_bench.byteswap": 3353148,
diff --git a/.github/cases/machamp/default.json b/.github/cases/machamp/default.json
index d7cde8503..79c384c88 100644
--- a/.github/cases/machamp/default.json
+++ b/.github/cases/machamp/default.json
@@ -23,128 +23,128 @@
   "codegen.vasub_vx": 250851,
   "codegen.vasubu_vv": 90595,
   "codegen.vasubu_vx": 250851,
-  "codegen.vcompress_vm": 32216,
+  "codegen.vcompress_vm": 32217,
   "codegen.vcpop_m": 1919,
-  "codegen.vdiv_vv": 33513,
+  "codegen.vdiv_vv": 33514,
   "codegen.vdiv_vx": 205363,
-  "codegen.vdivu_vv": 33523,
+  "codegen.vdivu_vv": 33524,
   "codegen.vdivu_vx": 214991,
   "codegen.vfirst_m": 1703,
-  "codegen.vid_v": 16078,
+  "codegen.vid_v": 16079,
   "codegen.viota_m": 64463,
-  "codegen.vl1re16_v": 691,
-  "codegen.vl1re32_v": 691,
-  "codegen.vl1re8_v": 691,
-  "codegen.vl2re16_v": 725,
-  "codegen.vl2re32_v": 725,
-  "codegen.vl2re8_v": 725,
-  "codegen.vl4re16_v": 793,
-  "codegen.vl4re32_v": 793,
-  "codegen.vl4re8_v": 793,
-  "codegen.vl8re16_v": 932,
-  "codegen.vl8re32_v": 929,
-  "codegen.vl8re8_v": 929,
+  "codegen.vl1re16_v": 692,
+  "codegen.vl1re32_v": 692,
+  "codegen.vl1re8_v": 692,
+  "codegen.vl2re16_v": 726,
+  "codegen.vl2re32_v": 726,
+  "codegen.vl2re8_v": 726,
+  "codegen.vl4re16_v": 794,
+  "codegen.vl4re32_v": 794,
+  "codegen.vl4re8_v": 794,
+  "codegen.vl8re16_v": 933,
+  "codegen.vl8re32_v": 930,
+  "codegen.vl8re8_v": 930,
   "codegen.vle16_v": 5089,
-  "codegen.vle16ff_v": 14480,
+  "codegen.vle16ff_v": 14481,
   "codegen.vle32_v": 4307,
-  "codegen.vle32ff_v": 8468,
+  "codegen.vle32ff_v": 8469,
   "codegen.vle8_v": 5808,
-  "codegen.vle8ff_v": 24083,
-  "codegen.vlm_v": 777,
+  "codegen.vle8ff_v": 24084,
+  "codegen.vlm_v": 778,
   "codegen.vloxei16_v": 40455,
-  "codegen.vloxei32_v": 21652,
-  "codegen.vloxei8_v": 58514,
-  "codegen.vloxseg2ei16_v": 40633,
+  "codegen.vloxei32_v": 21653,
+  "codegen.vloxei8_v": 58515,
+  "codegen.vloxseg2ei16_v": 40634,
   "codegen.vloxseg2ei32_v": 23028,
   "codegen.vloxseg2ei8_v": 54087,
-  "codegen.vloxseg3ei16_v": 29910,
-  "codegen.vloxseg3ei32_v": 17806,
-  "codegen.vloxseg3ei8_v": 39003,
-  "codegen.vloxseg4ei16_v": 35670,
+  "codegen.vloxseg3ei16_v": 29911,
+  "codegen.vloxseg3ei32_v": 17807,
+  "codegen.vloxseg3ei8_v": 39004,
+  "codegen.vloxseg4ei16_v": 35671,
   "codegen.vloxseg4ei32_v": 20271,
-  "codegen.vloxseg4ei8_v": 47466,
+  "codegen.vloxseg4ei8_v": 47467,
   "codegen.vloxseg5ei16_v": 21294,
-  "codegen.vloxseg5ei32_v": 8911,
-  "codegen.vloxseg5ei8_v": 29571,
+  "codegen.vloxseg5ei32_v": 8912,
+  "codegen.vloxseg5ei8_v": 29572,
   "codegen.vloxseg6ei16_v": 23910,
-  "codegen.vloxseg6ei32_v": 9584,
-  "codegen.vloxseg6ei8_v": 33630,
+  "codegen.vloxseg6ei32_v": 9585,
+  "codegen.vloxseg6ei8_v": 33631,
   "codegen.vloxseg7ei16_v": 26526,
-  "codegen.vloxseg7ei32_v": 10257,
-  "codegen.vloxseg7ei8_v": 37689,
+  "codegen.vloxseg7ei32_v": 10258,
+  "codegen.vloxseg7ei8_v": 37690,
   "codegen.vloxseg8ei16_v": 29142,
-  "codegen.vloxseg8ei32_v": 10930,
-  "codegen.vloxseg8ei8_v": 41748,
-  "codegen.vlse16_v": 66788,
-  "codegen.vlse32_v": 37553,
-  "codegen.vlse8_v": 114003,
+  "codegen.vloxseg8ei32_v": 10931,
+  "codegen.vloxseg8ei8_v": 41749,
+  "codegen.vlse16_v": 66789,
+  "codegen.vlse32_v": 37554,
+  "codegen.vlse8_v": 114004,
   "codegen.vlseg2e16_v": 4565,
   "codegen.vlseg2e32_v": 3692,
-  "codegen.vlseg2e8_v": 5394,
-  "codegen.vlseg3e16_v": 3884,
-  "codegen.vlseg3e32_v": 2823,
-  "codegen.vlseg3e8_v": 4876,
+  "codegen.vlseg2e8_v": 5395,
+  "codegen.vlseg3e16_v": 3885,
+  "codegen.vlseg3e32_v": 2824,
+  "codegen.vlseg3e8_v": 4877,
   "codegen.vlseg4e16_v": 4022,
   "codegen.vlseg4e32_v": 2923,
   "codegen.vlseg4e8_v": 5026,
-  "codegen.vlseg5e16_v": 3206,
+  "codegen.vlseg5e16_v": 3207,
   "codegen.vlseg5e32_v": 1778,
   "codegen.vlseg5e8_v": 4545,
-  "codegen.vlseg6e16_v": 3280,
-  "codegen.vlseg6e32_v": 1812,
+  "codegen.vlseg6e16_v": 3281,
+  "codegen.vlseg6e32_v": 1813,
   "codegen.vlseg6e8_v": 4635,
-  "codegen.vlseg7e16_v": 3354,
-  "codegen.vlseg7e32_v": 1846,
+  "codegen.vlseg7e16_v": 3355,
+  "codegen.vlseg7e32_v": 1847,
   "codegen.vlseg7e8_v": 4741,
-  "codegen.vlseg8e16_v": 3428,
+  "codegen.vlseg8e16_v": 3429,
   "codegen.vlseg8e32_v": 1878,
-  "codegen.vlseg8e8_v": 4827,
-  "codegen.vlsseg2e16_v": 60643,
-  "codegen.vlsseg2e32_v": 33148,
-  "codegen.vlsseg2e8_v": 114518,
-  "codegen.vlsseg3e16_v": 46898,
-  "codegen.vlsseg3e32_v": 21978,
-  "codegen.vlsseg3e8_v": 86983,
-  "codegen.vlsseg4e16_v": 57783,
-  "codegen.vlsseg4e32_v": 26028,
-  "codegen.vlsseg4e8_v": 109583,
-  "codegen.vlsseg5e16_v": 36398,
-  "codegen.vlsseg5e32_v": 11263,
-  "codegen.vlsseg5e8_v": 76843,
-  "codegen.vlsseg6e16_v": 41438,
-  "codegen.vlsseg6e32_v": 12378,
-  "codegen.vlsseg6e8_v": 88883,
-  "codegen.vlsseg7e16_v": 46478,
-  "codegen.vlsseg7e32_v": 13493,
-  "codegen.vlsseg7e8_v": 100923,
-  "codegen.vlsseg8e16_v": 51518,
-  "codegen.vlsseg8e32_v": 14608,
-  "codegen.vlsseg8e8_v": 112963,
+  "codegen.vlseg8e8_v": 4828,
+  "codegen.vlsseg2e16_v": 60644,
+  "codegen.vlsseg2e32_v": 33149,
+  "codegen.vlsseg2e8_v": 114519,
+  "codegen.vlsseg3e16_v": 46899,
+  "codegen.vlsseg3e32_v": 21979,
+  "codegen.vlsseg3e8_v": 86984,
+  "codegen.vlsseg4e16_v": 57784,
+  "codegen.vlsseg4e32_v": 26029,
+  "codegen.vlsseg4e8_v": 109584,
+  "codegen.vlsseg5e16_v": 36399,
+  "codegen.vlsseg5e32_v": 11264,
+  "codegen.vlsseg5e8_v": 76844,
+  "codegen.vlsseg6e16_v": 41439,
+  "codegen.vlsseg6e32_v": 12379,
+  "codegen.vlsseg6e8_v": 88884,
+  "codegen.vlsseg7e16_v": 46479,
+  "codegen.vlsseg7e32_v": 13494,
+  "codegen.vlsseg7e8_v": 100924,
+  "codegen.vlsseg8e16_v": 51519,
+  "codegen.vlsseg8e32_v": 14609,
+  "codegen.vlsseg8e8_v": 112964,
   "codegen.vluxei16_v": 40455,
-  "codegen.vluxei32_v": 21652,
-  "codegen.vluxei8_v": 58514,
-  "codegen.vluxseg2ei16_v": 40633,
+  "codegen.vluxei32_v": 21653,
+  "codegen.vluxei8_v": 58515,
+  "codegen.vluxseg2ei16_v": 40634,
   "codegen.vluxseg2ei32_v": 23028,
   "codegen.vluxseg2ei8_v": 54087,
-  "codegen.vluxseg3ei16_v": 29910,
-  "codegen.vluxseg3ei32_v": 17806,
-  "codegen.vluxseg3ei8_v": 39003,
-  "codegen.vluxseg4ei16_v": 35670,
+  "codegen.vluxseg3ei16_v": 29911,
+  "codegen.vluxseg3ei32_v": 17807,
+  "codegen.vluxseg3ei8_v": 39004,
+  "codegen.vluxseg4ei16_v": 35671,
   "codegen.vluxseg4ei32_v": 20271,
-  "codegen.vluxseg4ei8_v": 47466,
+  "codegen.vluxseg4ei8_v": 47467,
   "codegen.vluxseg5ei16_v": 21294,
-  "codegen.vluxseg5ei32_v": 8911,
-  "codegen.vluxseg5ei8_v": 29571,
+  "codegen.vluxseg5ei32_v": 8912,
+  "codegen.vluxseg5ei8_v": 29572,
   "codegen.vluxseg6ei16_v": 23910,
-  "codegen.vluxseg6ei32_v": 9584,
-  "codegen.vluxseg6ei8_v": 33630,
+  "codegen.vluxseg6ei32_v": 9585,
+  "codegen.vluxseg6ei8_v": 33631,
   "codegen.vluxseg7ei16_v": 26526,
-  "codegen.vluxseg7ei32_v": 10257,
-  "codegen.vluxseg7ei8_v": 37689,
+  "codegen.vluxseg7ei32_v": 10258,
+  "codegen.vluxseg7ei8_v": 37690,
   "codegen.vluxseg8ei16_v": 29142,
-  "codegen.vluxseg8ei32_v": 10930,
-  "codegen.vluxseg8ei8_v": 41748,
-  "codegen.vmacc_vv": 23371,
+  "codegen.vluxseg8ei32_v": 10931,
+  "codegen.vluxseg8ei8_v": 41749,
+  "codegen.vmacc_vv": 23372,
   "codegen.vmacc_vx": 76422,
   "codegen.vmadc_vi": 37536,
   "codegen.vmadc_vim": 38886,
@@ -152,10 +152,10 @@
   "codegen.vmadc_vvm": 12504,
   "codegen.vmadc_vx": 51738,
   "codegen.vmadc_vxm": 53088,
-  "codegen.vmadd_vv": 23371,
+  "codegen.vmadd_vv": 23372,
   "codegen.vmadd_vx": 76422,
-  "codegen.vmand_mm": 9979,
-  "codegen.vmandn_mm": 9979,
+  "codegen.vmand_mm": 9980,
+  "codegen.vmandn_mm": 9980,
   "codegen.vmax_vv": 22951,
   "codegen.vmax_vx": 63015,
   "codegen.vmaxu_vv": 22951,
@@ -167,93 +167,93 @@
   "codegen.vmin_vx": 63015,
   "codegen.vminu_vv": 22951,
   "codegen.vminu_vx": 63015,
-  "codegen.vmnand_mm": 9979,
-  "codegen.vmnor_mm": 9979,
-  "codegen.vmor_mm": 9979,
-  "codegen.vmorn_mm": 9979,
+  "codegen.vmnand_mm": 9980,
+  "codegen.vmnor_mm": 9980,
+  "codegen.vmor_mm": 9980,
+  "codegen.vmorn_mm": 9980,
   "codegen.vmsbc_vv": 11106,
   "codegen.vmsbc_vvm": 12456,
   "codegen.vmsbc_vx": 51738,
   "codegen.vmsbc_vxm": 53088,
-  "codegen.vmsbf_m": 1599,
+  "codegen.vmsbf_m": 1600,
   "codegen.vmseq_vi": 89192,
-  "codegen.vmseq_vv": 26198,
+  "codegen.vmseq_vv": 26199,
   "codegen.vmseq_vx": 122663,
   "codegen.vmsgt_vi": 89192,
-  "codegen.vmsgt_vv": 26131,
+  "codegen.vmsgt_vv": 26132,
   "codegen.vmsgt_vx": 122663,
   "codegen.vmsgtu_vi": 89192,
-  "codegen.vmsgtu_vv": 26131,
+  "codegen.vmsgtu_vv": 26132,
   "codegen.vmsgtu_vx": 122663,
-  "codegen.vmsif_m": 1599,
+  "codegen.vmsif_m": 1600,
   "codegen.vmsle_vi": 89192,
-  "codegen.vmsle_vv": 26198,
+  "codegen.vmsle_vv": 26199,
   "codegen.vmsle_vx": 122663,
   "codegen.vmsleu_vi": 89192,
-  "codegen.vmsleu_vv": 26198,
+  "codegen.vmsleu_vv": 26199,
   "codegen.vmsleu_vx": 122663,
-  "codegen.vmslt_vv": 26198,
+  "codegen.vmslt_vv": 26199,
   "codegen.vmslt_vx": 122663,
-  "codegen.vmsltu_vv": 26198,
+  "codegen.vmsltu_vv": 26199,
   "codegen.vmsltu_vx": 122663,
   "codegen.vmsne_vi": 89192,
-  "codegen.vmsne_vv": 26198,
+  "codegen.vmsne_vv": 26199,
   "codegen.vmsne_vx": 122663,
-  "codegen.vmsof_m": 1599,
-  "codegen.vmul_vv": 23254,
+  "codegen.vmsof_m": 1600,
+  "codegen.vmul_vv": 23255,
   "codegen.vmul_vx": 85688,
-  "codegen.vmulh_vv": 23254,
+  "codegen.vmulh_vv": 23255,
   "codegen.vmulh_vx": 85688,
-  "codegen.vmulhsu_vv": 23254,
+  "codegen.vmulhsu_vv": 23255,
   "codegen.vmulhsu_vx": 85688,
-  "codegen.vmulhu_vv": 23254,
+  "codegen.vmulhu_vv": 23255,
   "codegen.vmulhu_vx": 85688,
   "codegen.vmv_s_x": 1276,
   "codegen.vmv_v_i": 17636,
-  "codegen.vmv_v_v": 9886,
+  "codegen.vmv_v_v": 9887,
   "codegen.vmv_v_x": 7870,
   "codegen.vmv_x_s": 1753,
   "codegen.vmv1r_v": 1699,
   "codegen.vmv2r_v": 1805,
-  "codegen.vmv4r_v": 2044,
-  "codegen.vmv8r_v": 2525,
-  "codegen.vmxnor_mm": 9979,
-  "codegen.vmxor_mm": 9979,
+  "codegen.vmv4r_v": 2045,
+  "codegen.vmv8r_v": 2526,
+  "codegen.vmxnor_mm": 9980,
+  "codegen.vmxor_mm": 9980,
   "codegen.vnclip_wi": 154807,
-  "codegen.vnclip_wv": 60803,
+  "codegen.vnclip_wv": 60804,
   "codegen.vnclip_wx": 200311,
   "codegen.vnclipu_wi": 154807,
-  "codegen.vnclipu_wv": 60803,
+  "codegen.vnclipu_wv": 60804,
   "codegen.vnclipu_wx": 200311,
-  "codegen.vnmsac_vv": 23371,
+  "codegen.vnmsac_vv": 23372,
   "codegen.vnmsac_vx": 76422,
-  "codegen.vnmsub_vv": 23371,
+  "codegen.vnmsub_vv": 23372,
   "codegen.vnmsub_vx": 76422,
   "codegen.vnsra_wi": 39004,
-  "codegen.vnsra_wv": 15503,
+  "codegen.vnsra_wv": 15504,
   "codegen.vnsra_wx": 50380,
   "codegen.vnsrl_wi": 39004,
-  "codegen.vnsrl_wv": 15503,
+  "codegen.vnsrl_wv": 15504,
   "codegen.vnsrl_wx": 50380,
   "codegen.vor_vi": 49241,
   "codegen.vor_vv": 22951,
   "codegen.vor_vx": 63090,
-  "codegen.vredand_vs": 30831,
-  "codegen.vredmax_vs": 30831,
-  "codegen.vredmaxu_vs": 30831,
-  "codegen.vredmin_vs": 30831,
-  "codegen.vredminu_vs": 30831,
-  "codegen.vredor_vs": 30831,
-  "codegen.vredsum_vs": 30831,
-  "codegen.vredxor_vs": 30831,
-  "codegen.vrem_vv": 33513,
+  "codegen.vredand_vs": 30832,
+  "codegen.vredmax_vs": 30832,
+  "codegen.vredmaxu_vs": 30832,
+  "codegen.vredmin_vs": 30832,
+  "codegen.vredminu_vs": 30832,
+  "codegen.vredor_vs": 30832,
+  "codegen.vredsum_vs": 30832,
+  "codegen.vredxor_vs": 30832,
+  "codegen.vrem_vv": 33514,
   "codegen.vrem_vx": 205363,
-  "codegen.vremu_vv": 33523,
+  "codegen.vremu_vv": 33524,
   "codegen.vremu_vx": 214991,
   "codegen.vrgather_vi": 94651,
   "codegen.vrgather_vv": 178186,
   "codegen.vrgather_vx": 103069,
-  "codegen.vrgatherei16_vv": 133697,
+  "codegen.vrgatherei16_vv": 133698,
   "codegen.vrsub_vi": 49187,
   "codegen.vrsub_vx": 63015,
   "codegen.vs1r_v": 615,
@@ -271,10 +271,10 @@
   "codegen.vse16_v": 3957,
   "codegen.vse32_v": 3347,
   "codegen.vse8_v": 4567,
-  "codegen.vsetivli": 412,
-  "codegen.vsetvl": 412,
-  "codegen.vsetvli": 412,
-  "codegen.vsext_vf2": 39398,
+  "codegen.vsetivli": 413,
+  "codegen.vsetvl": 413,
+  "codegen.vsetvli": 413,
+  "codegen.vsext_vf2": 39399,
   "codegen.vsext_vf4": 6420,
   "codegen.vslide1down_vx": 1631019,
   "codegen.vslide1up_vx": 1625307,
@@ -286,9 +286,9 @@
   "codegen.vsll_vv": 25771,
   "codegen.vsll_vx": 81795,
   "codegen.vsm_v": 716,
-  "codegen.vsmul_vv": 91807,
+  "codegen.vsmul_vv": 91808,
   "codegen.vsmul_vx": 257803,
-  "codegen.vsoxei16_v": 38589,
+  "codegen.vsoxei16_v": 38590,
   "codegen.vsoxei32_v": 20261,
   "codegen.vsoxei8_v": 56641,
   "codegen.vsoxseg2ei16_v": 39058,
@@ -321,33 +321,33 @@
   "codegen.vsse16_v": 70079,
   "codegen.vsse32_v": 44219,
   "codegen.vsse8_v": 110603,
-  "codegen.vsseg2e16_v": 3643,
-  "codegen.vsseg2e32_v": 2945,
-  "codegen.vsseg2e8_v": 4341,
+  "codegen.vsseg2e16_v": 3644,
+  "codegen.vsseg2e32_v": 2946,
+  "codegen.vsseg2e8_v": 4342,
   "codegen.vsseg3e16_v": 3105,
   "codegen.vsseg3e32_v": 2279,
   "codegen.vsseg3e8_v": 3931,
-  "codegen.vsseg4e16_v": 3281,
-  "codegen.vsseg4e32_v": 2407,
-  "codegen.vsseg4e8_v": 4155,
+  "codegen.vsseg4e16_v": 3282,
+  "codegen.vsseg4e32_v": 2408,
+  "codegen.vsseg4e8_v": 4156,
   "codegen.vsseg5e16_v": 2567,
   "codegen.vsseg5e32_v": 1485,
   "codegen.vsseg5e8_v": 3649,
-  "codegen.vsseg6e16_v": 2663,
-  "codegen.vsseg6e32_v": 1533,
-  "codegen.vsseg6e8_v": 3793,
+  "codegen.vsseg6e16_v": 2664,
+  "codegen.vsseg6e32_v": 1534,
+  "codegen.vsseg6e8_v": 3794,
   "codegen.vsseg7e16_v": 2759,
   "codegen.vsseg7e32_v": 1581,
   "codegen.vsseg7e8_v": 3937,
-  "codegen.vsseg8e16_v": 2855,
-  "codegen.vsseg8e32_v": 1629,
-  "codegen.vsseg8e8_v": 4081,
-  "codegen.vssra_vi": 251063,
+  "codegen.vsseg8e16_v": 2856,
+  "codegen.vsseg8e32_v": 1630,
+  "codegen.vsseg8e8_v": 4082,
+  "codegen.vssra_vi": 251064,
   "codegen.vssra_vv": 101875,
-  "codegen.vssra_vx": 488655,
-  "codegen.vssrl_vi": 251063,
+  "codegen.vssra_vx": 488656,
+  "codegen.vssrl_vi": 251064,
   "codegen.vssrl_vv": 101875,
-  "codegen.vssrl_vx": 488655,
+  "codegen.vssrl_vx": 488656,
   "codegen.vssseg2e16_v": 63019,
   "codegen.vssseg2e32_v": 38351,
   "codegen.vssseg2e8_v": 109119,
@@ -375,7 +375,7 @@
   "codegen.vssubu_vx": 93444,
   "codegen.vsub_vv": 22951,
   "codegen.vsub_vx": 93444,
-  "codegen.vsuxei16_v": 38589,
+  "codegen.vsuxei16_v": 38590,
   "codegen.vsuxei32_v": 20261,
   "codegen.vsuxei8_v": 56641,
   "codegen.vsuxseg2ei16_v": 39058,
@@ -399,19 +399,19 @@
   "codegen.vsuxseg8ei16_v": 28922,
   "codegen.vsuxseg8ei32_v": 10443,
   "codegen.vsuxseg8ei8_v": 41900,
-  "codegen.vwadd_vv": 13856,
+  "codegen.vwadd_vv": 13857,
   "codegen.vwadd_vx": 39710,
   "codegen.vwadd_wv": 15217,
   "codegen.vwadd_wx": 46515,
-  "codegen.vwaddu_vv": 13856,
+  "codegen.vwaddu_vv": 13857,
   "codegen.vwaddu_vx": 39710,
   "codegen.vwaddu_wv": 15217,
   "codegen.vwaddu_wx": 46515,
-  "codegen.vwmacc_vv": 14785,
+  "codegen.vwmacc_vv": 14786,
   "codegen.vwmacc_vx": 57620,
-  "codegen.vwmaccsu_vv": 14785,
+  "codegen.vwmaccsu_vv": 14786,
   "codegen.vwmaccsu_vx": 57620,
-  "codegen.vwmaccu_vv": 14785,
+  "codegen.vwmaccu_vv": 14786,
   "codegen.vwmaccu_vx": 57620,
   "codegen.vwmaccus_vx": 57620,
   "codegen.vwmul_vv": 14000,
@@ -422,18 +422,18 @@
   "codegen.vwmulu_vx": 53468,
   "codegen.vwredsum_vs": 18435,
   "codegen.vwredsumu_vs": 18435,
-  "codegen.vwsub_vv": 13856,
+  "codegen.vwsub_vv": 13857,
   "codegen.vwsub_vx": 39710,
   "codegen.vwsub_wv": 15217,
   "codegen.vwsub_wx": 46515,
-  "codegen.vwsubu_vv": 13856,
+  "codegen.vwsubu_vv": 13857,
   "codegen.vwsubu_vx": 39710,
   "codegen.vwsubu_wv": 15217,
   "codegen.vwsubu_wx": 46515,
   "codegen.vxor_vi": 49241,
   "codegen.vxor_vv": 22951,
   "codegen.vxor_vx": 63090,
-  "codegen.vzext_vf2": 39398,
+  "codegen.vzext_vf2": 39399,
   "codegen.vzext_vf4": 6420,
   "rvv_bench.ascii_to_utf16": 1460078,
   "rvv_bench.ascii_to_utf32": 631187,
diff --git a/.github/cases/sandslash/default.json b/.github/cases/sandslash/default.json
index 32e69fe3a..c745b07cb 100644
--- a/.github/cases/sandslash/default.json
+++ b/.github/cases/sandslash/default.json
@@ -25,131 +25,131 @@
   "codegen.vasubu_vx": 336401,
   "codegen.vcompress_vm": 97701,
   "codegen.vcpop_m": 2681,
-  "codegen.vdiv_vv": 47995,
+  "codegen.vdiv_vv": 47996,
   "codegen.vdiv_vx": 342920,
   "codegen.vdivu_vv": 48248,
   "codegen.vdivu_vx": 359101,
   "codegen.vfirst_m": 2209,
-  "codegen.vid_v": 22148,
+  "codegen.vid_v": 22149,
   "codegen.viota_m": 194679,
-  "codegen.vl1re16_v": 1109,
-  "codegen.vl1re32_v": 1109,
-  "codegen.vl1re8_v": 1109,
-  "codegen.vl2re16_v": 1177,
-  "codegen.vl2re32_v": 1177,
-  "codegen.vl2re8_v": 1177,
-  "codegen.vl4re16_v": 1313,
-  "codegen.vl4re32_v": 1313,
-  "codegen.vl4re8_v": 1313,
-  "codegen.vl8re16_v": 1595,
-  "codegen.vl8re32_v": 1585,
-  "codegen.vl8re8_v": 1585,
+  "codegen.vl1re16_v": 1110,
+  "codegen.vl1re32_v": 1110,
+  "codegen.vl1re8_v": 1110,
+  "codegen.vl2re16_v": 1178,
+  "codegen.vl2re32_v": 1178,
+  "codegen.vl2re8_v": 1178,
+  "codegen.vl4re16_v": 1314,
+  "codegen.vl4re32_v": 1314,
+  "codegen.vl4re8_v": 1314,
+  "codegen.vl8re16_v": 1596,
+  "codegen.vl8re32_v": 1586,
+  "codegen.vl8re8_v": 1586,
   "codegen.vle16_v": 6965,
   "codegen.vle16ff_v": 40957,
-  "codegen.vle32_v": 6080,
-  "codegen.vle32ff_v": 21879,
-  "codegen.vle8_v": 7808,
+  "codegen.vle32_v": 6081,
+  "codegen.vle32ff_v": 21880,
+  "codegen.vle8_v": 7809,
   "codegen.vle8ff_v": 75462,
-  "codegen.vlm_v": 1482,
-  "codegen.vloxei16_v": 101085,
-  "codegen.vloxei32_v": 47404,
+  "codegen.vlm_v": 1483,
+  "codegen.vloxei16_v": 101086,
+  "codegen.vloxei32_v": 47405,
   "codegen.vloxei8_v": 166162,
-  "codegen.vloxseg2ei16_v": 108952,
-  "codegen.vloxseg2ei32_v": 56703,
-  "codegen.vloxseg2ei8_v": 158373,
-  "codegen.vloxseg3ei16_v": 81469,
-  "codegen.vloxseg3ei32_v": 43712,
-  "codegen.vloxseg3ei8_v": 112480,
-  "codegen.vloxseg4ei16_v": 103196,
+  "codegen.vloxseg2ei16_v": 108953,
+  "codegen.vloxseg2ei32_v": 56704,
+  "codegen.vloxseg2ei8_v": 158374,
+  "codegen.vloxseg3ei16_v": 81470,
+  "codegen.vloxseg3ei32_v": 43713,
+  "codegen.vloxseg3ei8_v": 112481,
+  "codegen.vloxseg4ei16_v": 103197,
   "codegen.vloxseg4ei32_v": 53554,
-  "codegen.vloxseg4ei8_v": 144408,
+  "codegen.vloxseg4ei8_v": 144409,
   "codegen.vloxseg5ei16_v": 57224,
-  "codegen.vloxseg5ei32_v": 25304,
-  "codegen.vloxseg5ei8_v": 90179,
+  "codegen.vloxseg5ei32_v": 25305,
+  "codegen.vloxseg5ei8_v": 90180,
   "codegen.vloxseg6ei16_v": 66325,
-  "codegen.vloxseg6ei32_v": 28714,
-  "codegen.vloxseg6ei8_v": 105594,
+  "codegen.vloxseg6ei32_v": 28715,
+  "codegen.vloxseg6ei8_v": 105595,
   "codegen.vloxseg7ei16_v": 75451,
-  "codegen.vloxseg7ei32_v": 32133,
-  "codegen.vloxseg7ei8_v": 121051,
+  "codegen.vloxseg7ei32_v": 32134,
+  "codegen.vloxseg7ei8_v": 121052,
   "codegen.vloxseg8ei16_v": 84552,
-  "codegen.vloxseg8ei32_v": 35543,
-  "codegen.vloxseg8ei8_v": 136466,
+  "codegen.vloxseg8ei32_v": 35544,
+  "codegen.vloxseg8ei8_v": 136467,
   "codegen.vlse16_v": 196925,
-  "codegen.vlse32_v": 102479,
+  "codegen.vlse32_v": 102480,
   "codegen.vlse8_v": 368506,
   "codegen.vlseg2e16_v": 6481,
   "codegen.vlseg2e32_v": 5446,
   "codegen.vlseg2e8_v": 7528,
-  "codegen.vlseg3e16_v": 5737,
-  "codegen.vlseg3e32_v": 4320,
-  "codegen.vlseg3e8_v": 7067,
+  "codegen.vlseg3e16_v": 5738,
+  "codegen.vlseg3e32_v": 4321,
+  "codegen.vlseg3e8_v": 7068,
   "codegen.vlseg4e16_v": 6039,
   "codegen.vlseg4e32_v": 4488,
   "codegen.vlseg4e8_v": 7415,
-  "codegen.vlseg5e16_v": 5049,
-  "codegen.vlseg5e32_v": 2919,
-  "codegen.vlseg5e8_v": 7096,
+  "codegen.vlseg5e16_v": 5050,
+  "codegen.vlseg5e32_v": 2920,
+  "codegen.vlseg5e8_v": 7097,
   "codegen.vlseg6e16_v": 5199,
   "codegen.vlseg6e32_v": 2983,
   "codegen.vlseg6e8_v": 7297,
   "codegen.vlseg7e16_v": 5346,
-  "codegen.vlseg7e32_v": 3047,
-  "codegen.vlseg7e8_v": 7498,
-  "codegen.vlseg8e16_v": 5497,
+  "codegen.vlseg7e32_v": 3048,
+  "codegen.vlseg7e8_v": 7499,
+  "codegen.vlseg8e16_v": 5498,
   "codegen.vlseg8e32_v": 3111,
   "codegen.vlseg8e8_v": 7699,
-  "codegen.vlsseg2e16_v": 184369,
-  "codegen.vlsseg2e32_v": 97273,
+  "codegen.vlsseg2e16_v": 184370,
+  "codegen.vlsseg2e32_v": 97274,
   "codegen.vlsseg2e8_v": 374215,
-  "codegen.vlsseg3e16_v": 142348,
-  "codegen.vlsseg3e32_v": 62352,
+  "codegen.vlsseg3e16_v": 142349,
+  "codegen.vlsseg3e32_v": 62353,
   "codegen.vlsseg3e8_v": 283284,
   "codegen.vlsseg4e16_v": 183288,
-  "codegen.vlsseg4e32_v": 78237,
-  "codegen.vlsseg4e8_v": 370769,
+  "codegen.vlsseg4e32_v": 78238,
+  "codegen.vlsseg4e8_v": 370770,
   "codegen.vlsseg5e16_v": 105177,
-  "codegen.vlsseg5e32_v": 37051,
+  "codegen.vlsseg5e32_v": 37052,
   "codegen.vlsseg5e8_v": 258898,
   "codegen.vlsseg6e16_v": 122687,
-  "codegen.vlsseg6e32_v": 42661,
+  "codegen.vlsseg6e32_v": 42662,
   "codegen.vlsseg6e8_v": 305253,
-  "codegen.vlsseg7e16_v": 140252,
-  "codegen.vlsseg7e32_v": 48271,
+  "codegen.vlsseg7e16_v": 140253,
+  "codegen.vlsseg7e32_v": 48272,
   "codegen.vlsseg7e8_v": 351748,
-  "codegen.vlsseg8e16_v": 157762,
-  "codegen.vlsseg8e32_v": 53881,
+  "codegen.vlsseg8e16_v": 157763,
+  "codegen.vlsseg8e32_v": 53882,
   "codegen.vlsseg8e8_v": 398103,
-  "codegen.vluxei16_v": 101085,
-  "codegen.vluxei32_v": 47404,
+  "codegen.vluxei16_v": 101086,
+  "codegen.vluxei32_v": 47405,
   "codegen.vluxei8_v": 166162,
-  "codegen.vluxseg2ei16_v": 108952,
-  "codegen.vluxseg2ei32_v": 56703,
-  "codegen.vluxseg2ei8_v": 158373,
-  "codegen.vluxseg3ei16_v": 81469,
-  "codegen.vluxseg3ei32_v": 43712,
-  "codegen.vluxseg3ei8_v": 112480,
-  "codegen.vluxseg4ei16_v": 103196,
+  "codegen.vluxseg2ei16_v": 108953,
+  "codegen.vluxseg2ei32_v": 56704,
+  "codegen.vluxseg2ei8_v": 158374,
+  "codegen.vluxseg3ei16_v": 81470,
+  "codegen.vluxseg3ei32_v": 43713,
+  "codegen.vluxseg3ei8_v": 112481,
+  "codegen.vluxseg4ei16_v": 103197,
   "codegen.vluxseg4ei32_v": 53554,
-  "codegen.vluxseg4ei8_v": 144408,
+  "codegen.vluxseg4ei8_v": 144409,
   "codegen.vluxseg5ei16_v": 57224,
-  "codegen.vluxseg5ei32_v": 25304,
-  "codegen.vluxseg5ei8_v": 90179,
+  "codegen.vluxseg5ei32_v": 25305,
+  "codegen.vluxseg5ei8_v": 90180,
   "codegen.vluxseg6ei16_v": 66325,
-  "codegen.vluxseg6ei32_v": 28714,
-  "codegen.vluxseg6ei8_v": 105594,
+  "codegen.vluxseg6ei32_v": 28715,
+  "codegen.vluxseg6ei8_v": 105595,
   "codegen.vluxseg7ei16_v": 75451,
-  "codegen.vluxseg7ei32_v": 32133,
-  "codegen.vluxseg7ei8_v": 121051,
+  "codegen.vluxseg7ei32_v": 32134,
+  "codegen.vluxseg7ei8_v": 121052,
   "codegen.vluxseg8ei16_v": 84552,
-  "codegen.vluxseg8ei32_v": 35543,
-  "codegen.vluxseg8ei8_v": 136466,
+  "codegen.vluxseg8ei32_v": 35544,
+  "codegen.vluxseg8ei8_v": 136467,
   "codegen.vmacc_vv": 31543,
   "codegen.vmacc_vx": 96318,
   "codegen.vmadc_vi": 57227,
   "codegen.vmadc_vim": 58847,
-  "codegen.vmadc_vv": 16562,
-  "codegen.vmadc_vvm": 18230,
+  "codegen.vmadc_vv": 16563,
+  "codegen.vmadc_vvm": 18231,
   "codegen.vmadc_vx": 78968,
   "codegen.vmadc_vxm": 80588,
   "codegen.vmadd_vv": 31543,
@@ -171,8 +171,8 @@
   "codegen.vmnor_mm": 13190,
   "codegen.vmor_mm": 13190,
   "codegen.vmorn_mm": 13190,
-  "codegen.vmsbc_vv": 16562,
-  "codegen.vmsbc_vvm": 18182,
+  "codegen.vmsbc_vv": 16563,
+  "codegen.vmsbc_vvm": 18183,
   "codegen.vmsbc_vx": 78968,
   "codegen.vmsbc_vxm": 80588,
   "codegen.vmsbf_m": 2105,
@@ -180,10 +180,10 @@
   "codegen.vmseq_vv": 42520,
   "codegen.vmseq_vx": 229999,
   "codegen.vmsgt_vi": 165628,
-  "codegen.vmsgt_vv": 42472,
+  "codegen.vmsgt_vv": 42473,
   "codegen.vmsgt_vx": 229999,
   "codegen.vmsgtu_vi": 165628,
-  "codegen.vmsgtu_vv": 42472,
+  "codegen.vmsgtu_vv": 42473,
   "codegen.vmsgtu_vx": 229999,
   "codegen.vmsif_m": 2105,
   "codegen.vmsle_vi": 165628,
@@ -200,40 +200,40 @@
   "codegen.vmsne_vv": 42520,
   "codegen.vmsne_vx": 229999,
   "codegen.vmsof_m": 2105,
-  "codegen.vmul_vv": 30739,
+  "codegen.vmul_vv": 30740,
   "codegen.vmul_vx": 114869,
-  "codegen.vmulh_vv": 30739,
+  "codegen.vmulh_vv": 30740,
   "codegen.vmulh_vx": 114869,
-  "codegen.vmulhsu_vv": 30739,
+  "codegen.vmulhsu_vv": 30740,
   "codegen.vmulhsu_vx": 114869,
-  "codegen.vmulhu_vv": 30739,
+  "codegen.vmulhu_vv": 30740,
   "codegen.vmulhu_vx": 114869,
   "codegen.vmv_s_x": 1718,
   "codegen.vmv_v_i": 27443,
-  "codegen.vmv_v_v": 13789,
+  "codegen.vmv_v_v": 13790,
   "codegen.vmv_v_x": 10940,
   "codegen.vmv_x_s": 2270,
   "codegen.vmv1r_v": 2189,
-  "codegen.vmv2r_v": 2428,
+  "codegen.vmv2r_v": 2429,
   "codegen.vmv4r_v": 3107,
-  "codegen.vmv8r_v": 4342,
+  "codegen.vmv8r_v": 4343,
   "codegen.vmxnor_mm": 13190,
   "codegen.vmxor_mm": 13190,
   "codegen.vnclip_wi": 216789,
-  "codegen.vnclip_wv": 78417,
+  "codegen.vnclip_wv": 78418,
   "codegen.vnclip_wx": 287441,
   "codegen.vnclipu_wi": 216789,
-  "codegen.vnclipu_wv": 78417,
+  "codegen.vnclipu_wv": 78418,
   "codegen.vnclipu_wx": 287441,
   "codegen.vnmsac_vv": 31543,
   "codegen.vnmsac_vx": 96318,
   "codegen.vnmsub_vv": 31543,
   "codegen.vnmsub_vx": 96318,
   "codegen.vnsra_wi": 54786,
-  "codegen.vnsra_wv": 20193,
+  "codegen.vnsra_wv": 20194,
   "codegen.vnsra_wx": 72449,
   "codegen.vnsrl_wi": 54786,
-  "codegen.vnsrl_wv": 20193,
+  "codegen.vnsrl_wv": 20194,
   "codegen.vnsrl_wx": 72449,
   "codegen.vor_vi": 65588,
   "codegen.vor_vv": 30354,
@@ -246,14 +246,14 @@
   "codegen.vredor_vs": 43949,
   "codegen.vredsum_vs": 43949,
   "codegen.vredxor_vs": 43949,
-  "codegen.vrem_vv": 47995,
+  "codegen.vrem_vv": 47996,
   "codegen.vrem_vx": 342920,
   "codegen.vremu_vv": 48248,
   "codegen.vremu_vx": 359101,
   "codegen.vrgather_vi": 132675,
   "codegen.vrgather_vv": 636093,
   "codegen.vrgather_vx": 154632,
-  "codegen.vrgatherei16_vv": 465563,
+  "codegen.vrgatherei16_vv": 465564,
   "codegen.vrsub_vi": 65413,
   "codegen.vrsub_vx": 84689,
   "codegen.vs1r_v": 1015,
@@ -271,11 +271,11 @@
   "codegen.vse16_v": 5499,
   "codegen.vse32_v": 4793,
   "codegen.vse8_v": 6205,
-  "codegen.vsetivli": 796,
-  "codegen.vsetvl": 796,
-  "codegen.vsetvli": 796,
+  "codegen.vsetivli": 797,
+  "codegen.vsetvl": 797,
+  "codegen.vsetvli": 797,
   "codegen.vsext_vf2": 134873,
-  "codegen.vsext_vf4": 19800,
+  "codegen.vsext_vf4": 19801,
   "codegen.vslide1down_vx": 6151877,
   "codegen.vslide1up_vx": 6146211,
   "codegen.vslidedown_vi": 4310885,
@@ -283,10 +283,10 @@
   "codegen.vslideup_vi": 4307448,
   "codegen.vslideup_vx": 6145386,
   "codegen.vsll_vi": 93945,
-  "codegen.vsll_vv": 35297,
+  "codegen.vsll_vv": 35298,
   "codegen.vsll_vx": 124250,
   "codegen.vsm_v": 1403,
-  "codegen.vsmul_vv": 120601,
+  "codegen.vsmul_vv": 120602,
   "codegen.vsmul_vx": 345113,
   "codegen.vsoxei16_v": 100017,
   "codegen.vsoxei32_v": 46463,
@@ -313,10 +313,10 @@
   "codegen.vsoxseg8ei32_v": 34741,
   "codegen.vsoxseg8ei8_v": 136706,
   "codegen.vsra_vi": 93945,
-  "codegen.vsra_vv": 35297,
+  "codegen.vsra_vv": 35298,
   "codegen.vsra_vx": 124250,
   "codegen.vsrl_vi": 93945,
-  "codegen.vsrl_vv": 35297,
+  "codegen.vsrl_vv": 35298,
   "codegen.vsrl_vx": 124250,
   "codegen.vsse16_v": 181937,
   "codegen.vsse32_v": 103133,
@@ -327,26 +327,26 @@
   "codegen.vsseg3e16_v": 4523,
   "codegen.vsseg3e32_v": 3437,
   "codegen.vsseg3e8_v": 5609,
-  "codegen.vsseg4e16_v": 4795,
-  "codegen.vsseg4e32_v": 3629,
-  "codegen.vsseg4e8_v": 5961,
+  "codegen.vsseg4e16_v": 4796,
+  "codegen.vsseg4e32_v": 3630,
+  "codegen.vsseg4e8_v": 5962,
   "codegen.vsseg5e16_v": 3917,
   "codegen.vsseg5e32_v": 2351,
   "codegen.vsseg5e8_v": 5483,
-  "codegen.vsseg6e16_v": 4077,
-  "codegen.vsseg6e32_v": 2431,
-  "codegen.vsseg6e8_v": 5723,
+  "codegen.vsseg6e16_v": 4078,
+  "codegen.vsseg6e32_v": 2432,
+  "codegen.vsseg6e8_v": 5724,
   "codegen.vsseg7e16_v": 4237,
   "codegen.vsseg7e32_v": 2511,
   "codegen.vsseg7e8_v": 5963,
-  "codegen.vsseg8e16_v": 4397,
-  "codegen.vsseg8e32_v": 2591,
-  "codegen.vsseg8e8_v": 6203,
+  "codegen.vsseg8e16_v": 4398,
+  "codegen.vsseg8e32_v": 2592,
+  "codegen.vsseg8e8_v": 6204,
   "codegen.vssra_vi": 373425,
-  "codegen.vssra_vv": 138833,
+  "codegen.vssra_vv": 138834,
   "codegen.vssra_vx": 748409,
   "codegen.vssrl_vi": 373425,
-  "codegen.vssrl_vv": 138833,
+  "codegen.vssrl_vv": 138834,
   "codegen.vssrl_vx": 748409,
   "codegen.vssseg2e16_v": 169369,
   "codegen.vssseg2e32_v": 96001,
@@ -401,40 +401,40 @@
   "codegen.vsuxseg8ei8_v": 136706,
   "codegen.vwadd_vv": 17925,
   "codegen.vwadd_vx": 53921,
-  "codegen.vwadd_wv": 19879,
+  "codegen.vwadd_wv": 19880,
   "codegen.vwadd_wx": 63094,
   "codegen.vwaddu_vv": 17925,
   "codegen.vwaddu_vx": 53921,
-  "codegen.vwaddu_wv": 19879,
+  "codegen.vwaddu_wv": 19880,
   "codegen.vwaddu_wx": 63094,
   "codegen.vwmacc_vv": 19365,
-  "codegen.vwmacc_vx": 72673,
+  "codegen.vwmacc_vx": 72674,
   "codegen.vwmaccsu_vv": 19365,
-  "codegen.vwmaccsu_vx": 72673,
+  "codegen.vwmaccsu_vx": 72674,
   "codegen.vwmaccu_vv": 19365,
-  "codegen.vwmaccu_vx": 72673,
-  "codegen.vwmaccus_vx": 72673,
-  "codegen.vwmul_vv": 18092,
+  "codegen.vwmaccu_vx": 72674,
+  "codegen.vwmaccus_vx": 72674,
+  "codegen.vwmul_vv": 18093,
   "codegen.vwmul_vx": 72112,
-  "codegen.vwmulsu_vv": 18092,
+  "codegen.vwmulsu_vv": 18093,
   "codegen.vwmulsu_vx": 72112,
-  "codegen.vwmulu_vv": 18092,
+  "codegen.vwmulu_vv": 18093,
   "codegen.vwmulu_vx": 72112,
   "codegen.vwredsum_vs": 26261,
   "codegen.vwredsumu_vs": 26261,
   "codegen.vwsub_vv": 17925,
   "codegen.vwsub_vx": 53921,
-  "codegen.vwsub_wv": 19879,
+  "codegen.vwsub_wv": 19880,
   "codegen.vwsub_wx": 63094,
   "codegen.vwsubu_vv": 17925,
   "codegen.vwsubu_vx": 53921,
-  "codegen.vwsubu_wv": 19879,
+  "codegen.vwsubu_wv": 19880,
   "codegen.vwsubu_wx": 63094,
   "codegen.vxor_vi": 65588,
   "codegen.vxor_vv": 30354,
   "codegen.vxor_vx": 84837,
   "codegen.vzext_vf2": 134873,
-  "codegen.vzext_vf4": 19800,
+  "codegen.vzext_vf4": 19801,
   "rvv_bench.ascii_to_utf16": 1371550,
   "rvv_bench.ascii_to_utf32": 583318,
   "rvv_bench.byteswap": 3556315,
diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
index 8826670d0..c38d5f9c9 100644
--- a/ipemu/src/TestBench.scala
+++ b/ipemu/src/TestBench.scala
@@ -33,7 +33,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
   val om: Property[ClassType] = IO(Output(Property[omType.Type]()))
   om := omInstance.getPropertyReference
 
-  lazy val clockGen = Module(new ExtModule with HasExtModuleInline {
+  val clockGen = Module(new ExtModule with HasExtModuleInline {
 
     override def desiredName = "ClockGen"
     setInline(
@@ -112,40 +112,38 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
   val issue = WireDefault(0.U.asTypeOf(new Issue))
   val fence = RegInit(false.B)
   val outstanding = RegInit(0.U(4.W))
-  val doIssue: Bool = dut.io.request.ready && !fence
-  outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.response.valid
-  fence := Mux(doIssue, issue.meta === 2.U, fence && !dut.io.response.valid && !(outstanding === 0.U))
+  val doIssue: Bool = dut.io.issue.ready && !fence
+  outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid
+  // TODO: refactor driver to spawn 3 scoreboards for record different retirement.
+  val t1Probe = probe.read(dut.io.t1Probe)
+  fence := Mux(doIssue, issue.meta === 2.U, fence && !t1Probe.retireValid && !(outstanding === 0.U))
 
   issue := RawClockedNonVoidFunctionCall("issue_vector_instruction", new Issue)(
     clock,
     doIssue
   )
-  dut.io.request.bits.instruction := issue.instruction
-  dut.io.request.bits.src1Data := issue.src1Data
-  dut.io.request.bits.src2Data := issue.src2Data
-  dut.io.csrInterface.vlmul := issue.vtype(2, 0)
-  dut.io.csrInterface.vSew := issue.vtype(5, 3)
-  dut.io.csrInterface.vta := issue.vtype(6)
-  dut.io.csrInterface.vma := issue.vtype(7)
-  dut.io.csrInterface.vl := issue.vl
-  dut.io.csrInterface.vStart := issue.vstart
-  dut.io.csrInterface.vxrm := issue.vcsr(2, 1)
-
-  dut.io.csrInterface.ignoreException := 0.U
-  dut.io.storeBufferClear := true.B
-  dut.io.request.valid := issue.meta === 1.U
+  dut.io.issue.bits.instruction := issue.instruction
+  dut.io.issue.bits.rs1Data := issue.src1Data
+  dut.io.issue.bits.rs2Data := issue.src2Data
+  dut.io.issue.bits.vtype := issue.vtype
+  dut.io.issue.bits.vl := issue.vl
+  dut.io.issue.bits.vstart := issue.vstart
+  dut.io.issue.bits.vcsr := issue.vcsr
+  dut.io.issue.valid := issue.meta === 1.U
   when(issue.meta =/= 0.U && issue.meta =/= 1.U && issue.meta =/= 2.U) {
     stop(cf"""{"event":"SimulationStop","reason": ${issue.meta},"cycle":${simulationTime}}\n""")
   }
   val retire = Wire(new Retire)
-  retire.rd := dut.io.response.bits.rd.bits
-  retire.data := dut.io.response.bits.data
-  retire.writeRd := dut.io.response.bits.rd.valid
-  retire.vxsat := dut.io.response.bits.vxsat
-  RawClockedVoidFunctionCall("retire_vector_instruction")(clock, dut.io.response.valid, retire)
+  retire.rd := dut.io.retire.rd.bits.rdAddress
+  retire.data := dut.io.retire.rd.bits.rdData
+  retire.writeRd := dut.io.retire.rd.valid
+  retire.vxsat := dut.io.retire.csr.bits.vxsat
+  // TODO:
+  //  retire.fflag := dut.io.retire.csr.bits.fflag
+  RawClockedVoidFunctionCall("retire_vector_instruction")(clock, t1Probe.retireValid, retire)
   val dummy = Wire(Bool())
   dummy := false.B
-  RawClockedVoidFunctionCall("retire_vector_mem")(clock, dut.io.response.bits.mem && dut.io.response.valid, dummy)
+  RawClockedVoidFunctionCall("retire_vector_mem")(clock, dut.io.retire.mem.valid, dummy)
 
   // Memory Drivers
   Seq(
@@ -201,8 +199,6 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
       wire
   }
 
-  val t1Probe = probe.read(dut.io.t1Probe)
-
   // vrf write
   laneVrfProbes.zipWithIndex.foreach {
     case (lane, i) =>
@@ -225,13 +221,13 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
     )
   )
   // issue
-  when(dut.io.request.fire)(
+  when(dut.io.issue.fire)(
     printf(cf"""{"event":"Issue","idx":${t1Probe.instructionCounter},"cycle":${simulationTime}}\n""")
   )
   // check rd
-  when(dut.io.response.bits.rd.valid)(
+  when(dut.io.retire.rd.valid)(
     printf(
-      cf"""{"event":"CheckRd","data":"${dut.io.response.bits.data}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n"""
+      cf"""{"event":"CheckRd","data":"${dut.io.retire.rd.bits.rdData}%x","issue_idx":${t1Probe.responseCounter},"cycle":${simulationTime}}\n"""
     )
   )
   // lsu enq
diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
index fb79e2af3..bb8a36f41 100644
--- a/t1/src/Bundles.scala
+++ b/t1/src/Bundles.scala
@@ -10,23 +10,6 @@ import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.LSUParameter
 import org.chipsalliance.t1.rtl.vrf.VRFParam
 
-/** Interface from CPU. */
-class VRequest(xLen: Int) extends Bundle {
-
-  /** instruction fetched by scalar processor. */
-  val instruction: UInt = UInt(32.W)
-
-  /** data read from scalar RF RS1.
-    * TODO: rename to rs1Data
-    */
-  val src1Data: UInt = UInt(xLen.W)
-
-  /** data read from scalar RF RS2.
-    * TODO: rename to rs2Data
-    */
-  val src2Data: UInt = UInt(xLen.W)
-}
-
 /** Interface to CPU. */
 class VResponse(xLen: Int) extends Bundle {
 
@@ -325,9 +308,6 @@ class CSRInterface(vlWidth: Int) extends Bundle {
     * we always keep the undisturbed behavior, since there is no rename here.
     */
   val vma: Bool = Bool()
-
-  /** TODO: remove it. */
-  val ignoreException: Bool = Bool()
 }
 
 /** [[Lane]] -> [[T1]], response for [[LaneRequest]] */
@@ -501,20 +481,11 @@ class VRFWriteReport(param: VRFParam) extends Bundle {
   val state = new VRFInstructionState
 }
 
-/** 为了decode, 指令需要在入口的时候打一拍, 这是需要保存的信息 */
 class InstructionPipeBundle(parameter: T1Parameter) extends Bundle {
-  // 原始指令信息
-  val request: VRequest = new VRequest(parameter.xLen)
-  // decode 的结果
+  val issue: T1Issue = new T1Issue(parameter.xLen, parameter.vLen)
   val decodeResult: DecodeBundle = new DecodeBundle(Decoder.allFields(parameter.decoderParam))
-  // 这条指令被vector分配的index
   val instructionIndex: UInt = UInt(parameter.instructionIndexBits.W)
-  // 指令的csr信息
-  val csr = new CSRInterface(parameter.laneParam.vlMaxBits)
-  // 有写v0的风险
   val vdIsV0: Bool = Bool()
-
-  // How many bytes of registers will be written by one instruction?
   val writeByte: UInt = UInt(parameter.laneParam.vlMaxBits.W)
 }
 
@@ -711,3 +682,44 @@ final class EmptyBundle extends Bundle
 class VRFReadPipe(size: BigInt) extends Bundle {
   val address: UInt = UInt(log2Ceil(size).W)
 }
+
+class T1Issue(xLen: Int, vlWidth: Int) extends Bundle {
+
+  /** instruction fetched by scalar processor. */
+  val instruction: UInt = UInt(32.W)
+
+  /** data read from scalar RF RS1. */
+  val rs1Data: UInt = UInt(xLen.W)
+
+  /** data read from scalar RF RS2. */
+  val rs2Data: UInt = UInt(xLen.W)
+  val vtype: UInt = UInt(32.W)
+  val vl:    UInt = UInt(32.W)
+  val vstart: UInt = UInt(32.W)
+  val vcsr: UInt = UInt(32.W)
+}
+
+object T1Issue {
+  def vlmul(issue: T1Issue) = issue.vtype(2, 0)
+  def vsew(issue: T1Issue) = issue.vtype(5, 3)
+  def vta(issue: T1Issue) = issue.vtype(6)
+  def vma(issue: T1Issue) = issue.vtype(7)
+  def vxrm(issue: T1Issue) = issue.vcsr(2, 1)
+}
+
+class T1RdRetire(xLen: Int) extends Bundle {
+  val rdAddress: UInt = UInt(5.W)
+  val rdData:    UInt = UInt(xLen.W)
+  val isFp:      Bool = Bool()
+}
+
+class T1CSRRetire extends Bundle {
+  val vxsat: UInt = UInt(32.W)
+  val fflag: UInt = UInt(32.W)
+}
+
+class T1Retire(xLen: Int) extends Bundle {
+  val rd:  ValidIO[T1RdRetire] = Valid(new T1RdRetire(xLen))
+  val csr: ValidIO[T1CSRRetire] = Valid(new T1CSRRetire)
+  val mem: ValidIO[EmptyBundle] = Valid(new EmptyBundle)
+}
\ No newline at end of file
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index 901a11f24..64daf2ddc 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -276,6 +276,7 @@ class T1Probe(param: T1Parameter) extends Bundle {
   val instructionCounter: UInt = UInt(param.instructionIndexBits.W)
   val instructionIssue: Bool = Bool()
   val issueTag: UInt = UInt(param.instructionIndexBits.W)
+  val retireValid: Bool = Bool()
   // write queue enq for mask unit
   val writeQueueEnq: ValidIO[UInt] = Valid(UInt(param.instructionIndexBits.W))
   val writeQueueEnqMask: UInt = UInt((param.datapathWidth / 8).W)
@@ -288,34 +289,22 @@ class T1Probe(param: T1Parameter) extends Bundle {
 class T1Interface(parameter: T1Parameter) extends Record {
   def clock = elements("clock").asInstanceOf[Clock]
   def reset = elements("reset").asInstanceOf[Bool]
-  /** request from CPU.
-    * because the interrupt and exception of previous instruction is unpredictable,
-    * and the `kill` logic in Vector processor is too high,
-    * thus the request should come from commit stage to avoid any interrupt or excepiton.
-    */
-  def request = elements("request").asInstanceOf[DecoupledIO[VRequest]]
-  /** response to CPU. */
-  def response: ValidIO[VResponse] = elements("response").asInstanceOf[ValidIO[VResponse]]
-  /** CSR interface from CPU. */
-  def csrInterface: CSRInterface = elements("csrInterface").asInstanceOf[CSRInterface]
-  /** from CPU LSU, store buffer is cleared, memory can observe memory requests after this is asserted. */
-  def storeBufferClear: Bool = elements("storeBufferClear").asInstanceOf[Bool]
+  def issue = elements("issue").asInstanceOf[DecoupledIO[T1Issue]]
+  def retire = elements("retire").asInstanceOf[T1Retire]
   def highBandwidthLoadStorePort: AXI4RWIrrevocable = elements("highBandwidthLoadStorePort").asInstanceOf[AXI4RWIrrevocable]
   def indexedLoadStorePort: AXI4RWIrrevocable = elements("indexedLoadStorePort").asInstanceOf[AXI4RWIrrevocable]
   def om: Property[ClassType] = elements("om").asInstanceOf[Property[ClassType]]
+  // TODO: refactor to an single Probe to avoid using Record on the [[T1Interface]].
   def lsuProbe: LSUProbe = elements("lsuProbe").asInstanceOf[LSUProbe]
   def t1Probe: T1Probe = elements("t1Probe").asInstanceOf[T1Probe]
   def laneProbes: Seq[LaneProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}Probe").asInstanceOf[LaneProbe])
   def laneVrfProbes: Seq[VRFProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}VrfProbe").asInstanceOf[VRFProbe])
-
   val elements: SeqMap[String, Data] = SeqMap.from(
     Seq(
       "clock" -> Input(Clock()),
       "reset" -> Input(Bool()),
-      "request" -> Flipped(Decoupled(new VRequest(parameter.xLen))),
-      "response" -> Valid(new VResponse(parameter.xLen)),
-      "csrInterface" -> Input(new CSRInterface(parameter.laneParam.vlMaxBits)),
-      "storeBufferClear" -> Input(Bool()),
+      "issue" -> Flipped(Decoupled(new T1Issue(parameter.xLen, parameter.vLen))),
+      "retire" -> new T1Retire(parameter.xLen),
       "highBandwidthLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter),
       "indexedLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter.copy(dataWidth=32)),
       "om" -> Output(Property[AnyClassType]()),
@@ -362,39 +351,46 @@ class T1(val parameter: T1Parameter)
   // TODO: uarch doc about the order of instructions
   val instructionCounter:     UInt = RegInit(0.U(parameter.instructionIndexBits.W))
   val nextInstructionCounter: UInt = instructionCounter + 1.U
-  when(io.request.fire) { instructionCounter := nextInstructionCounter }
+  when(io.issue.fire) { instructionCounter := nextInstructionCounter }
 
+  val retire = WireDefault(false.B)
   // todo: handle waw
   val responseCounter:     UInt = RegInit(0.U(parameter.instructionIndexBits.W))
   val nextResponseCounter: UInt = responseCounter + 1.U
-  when(io.response.fire) { responseCounter := nextResponseCounter }
+  when(retire) { responseCounter := nextResponseCounter }
 
   // maintained a 1 depth queue for VRequest.
   // TODO: directly maintain a `ready` signal
   /** register to latch instruction. */
   val requestReg: ValidIO[InstructionPipeBundle] = RegInit(0.U.asTypeOf(Valid(new InstructionPipeBundle(parameter))))
-
+  val requestRegCSR: CSRInterface = WireDefault(0.U.asTypeOf(new CSRInterface(parameter.laneParam.vlMaxBits)))
+  requestRegCSR.vlmul := requestReg.bits.issue.vtype(2, 0)
+  requestRegCSR.vSew := requestReg.bits.issue.vtype(5, 3)
+  requestRegCSR.vta := requestReg.bits.issue.vtype(6)
+  requestRegCSR.vma := requestReg.bits.issue.vtype(7)
+  requestRegCSR.vl := requestReg.bits.issue.vl
+  requestRegCSR.vStart := requestReg.bits.issue.vstart
+  requestRegCSR.vxrm := requestReg.bits.issue.vcsr(2, 1)
   /** maintain a [[DecoupleIO]] for [[requestReg]]. */
-  val requestRegDequeue = Wire(Decoupled(new VRequest(parameter.xLen)))
+  val requestRegDequeue = Wire(Decoupled(new T1Issue(parameter.xLen, parameter.vLen)))
   // latch instruction, csr, decode result and instruction index to requestReg.
-  when(io.request.fire) {
+  when(io.issue.fire) {
     // The LSU only need to know the instruction, and don't need information from decoder.
     // Thus we latch the request here, and send it to LSU.
-    requestReg.bits.request := io.request.bits
+    requestReg.bits.issue := io.issue.bits
     requestReg.bits.decodeResult := decode.decodeResult
-    requestReg.bits.csr := io.csrInterface
     requestReg.bits.instructionIndex := instructionCounter
     // vd === 0 && not store type
-    requestReg.bits.vdIsV0 := (io.request.bits.instruction(11, 7) === 0.U) &&
-      (io.request.bits.instruction(6) || !io.request.bits.instruction(5))
+    requestReg.bits.vdIsV0 := (io.issue.bits.instruction(11, 7) === 0.U) &&
+      (io.issue.bits.instruction(6) || !io.issue.bits.instruction(5))
     requestReg.bits.writeByte := Mux(
       decode.decodeResult(Decoder.red),
       // Must be smaller than dataPath
       1.U,
       Mux(
         decode.decodeResult(Decoder.maskDestination),
-        (io.csrInterface.vl >> 3).asUInt + io.csrInterface.vl(2, 0).orR,
-        io.csrInterface.vl << (io.csrInterface.vSew + decode.decodeResult(Decoder.crossWrite))
+        (io.issue.bits.vl >> 3).asUInt + io.issue.bits.vl(2, 0).orR,
+        io.issue.bits.vl << (T1Issue.vsew(io.issue.bits) + decode.decodeResult(Decoder.crossWrite))
       )
     )
   }
@@ -402,17 +398,16 @@ class T1(val parameter: T1Parameter)
   // 0 1 -> update to false
   // 1 0 -> update to true
   // 1 1 -> don't update
-  requestReg.valid := Mux(io.request.fire ^ requestRegDequeue.fire, io.request.fire, requestReg.valid)
+  requestReg.valid := Mux(io.issue.fire ^ requestRegDequeue.fire, io.issue.fire, requestReg.valid)
   // ready when requestReg is free or it will be free in this cycle.
-  io.request.ready := !requestReg.valid || requestRegDequeue.ready
+  io.issue.ready := !requestReg.valid || requestRegDequeue.ready
   // manually maintain a queue for requestReg.
-  requestRegDequeue.bits := requestReg.bits.request
+  requestRegDequeue.bits := requestReg.bits.issue
   requestRegDequeue.valid := requestReg.valid
-  decode.decodeInput := io.request.bits.instruction
+  decode.decodeInput := io.issue.bits.instruction
 
   /** alias to [[requestReg.bits.decodeResult]], it is commonly used. */
   val decodeResult: DecodeBundle = requestReg.bits.decodeResult
-  // 这是当前正在mask unit 里面的那一条指令的csr信息,用来计算mask unit的控制信号
   val csrRegForMaskUnit: CSRInterface = RegInit(0.U.asTypeOf(new CSRInterface(parameter.laneParam.vlMaxBits)))
   val vSewOHForMask: UInt = UIntToOH(csrRegForMaskUnit.vSew)(2, 0)
 
@@ -428,26 +423,26 @@ class T1(val parameter: T1Parameter)
   // 只进mask unit的指令
   val maskUnitInstruction: Bool = (decodeResult(Decoder.slid) || decodeResult(Decoder.mv))
   val skipLastFromLane: Bool = isLoadStoreType || maskUnitInstruction || readOnlyInstruction
-  val instructionValid: Bool = requestReg.bits.csr.vl > requestReg.bits.csr.vStart
+  val instructionValid: Bool = requestReg.bits.issue.vl > requestReg.bits.issue.vstart
 
   // TODO: these should be decoding results
   /** load store that don't read offset. */
   val noOffsetReadLoadStore: Bool = isLoadStoreType && (!requestRegDequeue.bits.instruction(26))
 
-  val vSew1H: UInt = UIntToOH(requestReg.bits.csr.vSew)
+  val vSew1H: UInt = UIntToOH(T1Issue.vsew(requestReg.bits.issue))
   val source1Extend: UInt = Mux1H(
     vSew1H(2, 0),
     Seq(
-      Fill(parameter.datapathWidth - 8, requestRegDequeue.bits.src1Data(7) && !decodeResult(Decoder.unsigned0))
-        ## requestRegDequeue.bits.src1Data(7, 0),
-      Fill(parameter.datapathWidth - 16, requestRegDequeue.bits.src1Data(15) && !decodeResult(Decoder.unsigned0))
-        ## requestRegDequeue.bits.src1Data(15, 0),
-      requestRegDequeue.bits.src1Data(31, 0)
+      Fill(parameter.datapathWidth - 8, requestRegDequeue.bits.rs1Data(7) && !decodeResult(Decoder.unsigned0))
+        ## requestRegDequeue.bits.rs1Data(7, 0),
+      Fill(parameter.datapathWidth - 16, requestRegDequeue.bits.rs1Data(15) && !decodeResult(Decoder.unsigned0))
+        ## requestRegDequeue.bits.rs1Data(15, 0),
+      requestRegDequeue.bits.rs1Data(31, 0)
     )
   )
   /** src1 from scalar core is a signed number. */
   val src1IsSInt: Bool = !requestReg.bits.decodeResult(Decoder.unsigned0)
-  val imm: UInt = requestReg.bits.request.instruction(19, 15)
+  val imm: UInt = requestReg.bits.issue.instruction(19, 15)
   // todo: spec 10.1: imm 默认是 sign-extend,但是有特殊情况
   val immSignExtend: UInt = Fill(16, imm(4) && (vSew1H(2) || src1IsSInt)) ##
     Fill(8, imm(4) && (vSew1H(1) || vSew1H(2) || src1IsSInt)) ##
@@ -647,7 +642,7 @@ class T1(val parameter: T1Parameter)
           control.state.wVRFWrite := true.B
         }
 
-        when(responseCounter === control.record.instructionIndex && io.response.fire) {
+        when(responseCounter === control.record.instructionIndex && retire) {
           control.state.sCommit := true.B
         }
 
@@ -705,12 +700,12 @@ class T1(val parameter: T1Parameter)
       // first type instruction
       val firstLane = ffo(completedVec.asUInt)
       val firstLaneIndex: UInt = OHToUInt(firstLane)(log2Ceil(parameter.laneNumber) - 1, 0)
-      io.response.bits.rd.valid := lastSlotCommit && decodeResultReg(Decoder.targetRd)
-      io.response.bits.rd.bits := vd
+      io.retire.rd.valid := lastSlotCommit && decodeResultReg(Decoder.targetRd)
+      io.retire.rd.bits.rdAddress := vd
       if (parameter.fpuEnable) {
-        io.response.bits.float := decodeResultReg(Decoder.float)
+        io.retire.rd.bits.isFp := decodeResultReg(Decoder.float)
       } else {
-        io.response.bits.float := false.B
+        io.retire.rd.bits.isFp := false.B
       }
       when(requestRegDequeue.fire) {
         ffoIndexReg.valid := false.B
@@ -733,7 +728,7 @@ class T1(val parameter: T1Parameter)
         * lmul - sew <- [-5, 3]
         * 选择信号 +5 -> lmul - sew + 5 <- [0, 8]
         */
-      def largeThanVLMax(source: UInt, advance: Bool = false.B, csrInput:CSRInterface): Bool = {
+      def largeThanVLMax(source: UInt, advance: Bool = false.B, lmul: UInt, sew: UInt): Bool = {
         val vlenLog2 = log2Ceil(parameter.vLen) // 10
         val cut =
           if (source.getWidth >= vlenLog2) source(vlenLog2 - 1, vlenLog2 - 9)
@@ -745,15 +740,15 @@ class T1(val parameter: T1Parameter)
             largeList(i) := a
             a || b
         }
-        val extendVlmul = csrInput.vlmul(2) ## csrInput.vlmul
-        val selectWire = UIntToOH(5.U(4.W) + extendVlmul - csrInput.vSew)(8, 0).asBools.reverse
+        val extendVlmul = lmul(2) ## lmul
+        val selectWire = UIntToOH(5.U(4.W) + extendVlmul - sew)(8, 0).asBools.reverse
         Mux1H(selectWire, largeList)
       }
       // 算req上面的分开吧
       val gatherWire =
-        Mux(decodeResult(Decoder.itype), requestRegDequeue.bits.instruction(19, 15), requestRegDequeue.bits.src1Data)
+        Mux(decodeResult(Decoder.itype), requestRegDequeue.bits.instruction(19, 15), requestRegDequeue.bits.rs1Data)
       val gatherAdvance = (gatherWire >> log2Ceil(parameter.vLen)).asUInt.orR
-      gatherOverlap := largeThanVLMax(gatherWire, gatherAdvance, requestReg.bits.csr)
+      gatherOverlap := largeThanVLMax(gatherWire, gatherAdvance, T1Issue.vlmul(requestReg.bits.issue), T1Issue.vsew(requestReg.bits.issue))
       val slotValid = !control.state.idle
       val storeAfterSlide = isStoreType && (requestRegDequeue.bits.instruction(11, 7) === vd)
       instructionRAWReady := !((unOrderTypeInstruction && slotValid &&
@@ -783,9 +778,9 @@ class T1(val parameter: T1Parameter)
         vs2 := requestRegDequeue.bits.instruction(24, 20)
         vm := requestRegDequeue.bits.instruction(25)
         executeFinishReg := false.B
-        rs1 := requestRegDequeue.bits.src1Data
+        rs1 := requestRegDequeue.bits.rs1Data
         decodeResultReg := decodeResult
-        csrRegForMaskUnit := requestReg.bits.csr
+        csrRegForMaskUnit := requestRegCSR
         // todo: decode need execute
         control.state.sMaskUnitExecution := !maskUnitType
         maskTypeInstruction := maskType && !decodeResult(Decoder.maskSource)
@@ -987,7 +982,7 @@ class T1(val parameter: T1Parameter)
 
       val compareWire = Mux(decodeResultReg(Decoder.slid), rs1, maskUnitData)
       val compareAdvance: Bool = (compareWire >> log2Ceil(parameter.vLen)).asUInt.orR
-      val compareResult:  Bool = largeThanVLMax(compareWire, compareAdvance, csrRegForMaskUnit)
+      val compareResult:  Bool = largeThanVLMax(compareWire, compareAdvance, csrRegForMaskUnit.vlmul, csrRegForMaskUnit.vSew)
       // 正在被gather使用的数据在data的那个组里
       val gatherDataSelect = UIntToOH((false.B ## maskUnitDataOffset)(5 + (log2Ceil(parameter.laneNumber) max 1) - 1, 5))
       val dataTail = Mux1H(UIntToOH(maskUnitEEW)(1, 0), Seq(3.U(2.W), 2.U(2.W)))
@@ -1072,7 +1067,7 @@ class T1(val parameter: T1Parameter)
       // index >= vlMax 是写0
       val overlapVlMax: Bool = !slideUp && (signBit || srcOversize)
       // select csr
-      val csrSelect = Mux(control.state.idle, requestReg.bits.csr, csrRegForMaskUnit)
+      val csrSelect = Mux(control.state.idle, requestRegCSR, csrRegForMaskUnit)
       // slid read
       val (_, readDataOffset, readLane, readOffset, readGrowth, lmulOverlap) = indexAnalysis(readIndex, csrSelect)
       gatherReadDataOffset := readDataOffset
@@ -1434,7 +1429,7 @@ class T1(val parameter: T1Parameter)
     Mux(
       decodeResult(Decoder.nr) || decodeResult(Decoder.maskLogic),
       2.U,
-      Mux(gather16, 1.U, Mux(decodeResult(Decoder.extend), extendDataEEW, requestReg.bits.csr.vSew))
+      Mux(gather16, 1.U, Mux(decodeResult(Decoder.extend), extendDataEEW, T1Issue.vsew(requestReg.bits.issue)))
     )
   )
 
@@ -1442,14 +1437,14 @@ class T1(val parameter: T1Parameter)
     decodeResult(Decoder.nr),
     // evl for Whole Vector Register Move ->  vs1 * (vlen / datapathWidth)
     (requestRegDequeue.bits.instruction(17, 15) +& 1.U) ## 0.U(log2Ceil(parameter.vLen / parameter.datapathWidth).W),
-    requestReg.bits.csr.vl
+    requestReg.bits.issue.vl
   )
 
   val vSewForLsu: UInt = Mux(lsWholeReg, 2.U, requestRegDequeue.bits.instruction(13, 12))
   val evlForLsu: UInt = Mux(
     lsWholeReg,
     (requestRegDequeue.bits.instruction(31, 29) +& 1.U) ## 0.U(log2Ceil(parameter.vLen / parameter.datapathWidth).W),
-    requestReg.bits.csr.vl
+    requestReg.bits.issue.vl
   )
 
   /** instantiate lanes.
@@ -1489,7 +1484,7 @@ class T1(val parameter: T1Parameter)
     lane.laneRequest.bits.mask := maskType
     laneReady(index) := lane.laneRequest.ready
 
-    lane.csrInterface := requestReg.bits.csr
+    lane.csrInterface := requestRegCSR
     // index type EEW Decoded in the instruction
     lane.csrInterface.vSew := vSewSelect
     lane.csrInterface.vl := evlForLane
@@ -1580,8 +1575,8 @@ class T1(val parameter: T1Parameter)
   // 连lsu
   lsu.request.valid := requestRegDequeue.fire && isLoadStoreType
   lsu.request.bits.instructionIndex := requestReg.bits.instructionIndex
-  lsu.request.bits.rs1Data := requestRegDequeue.bits.src1Data
-  lsu.request.bits.rs2Data := requestRegDequeue.bits.src2Data
+  lsu.request.bits.rs1Data := requestRegDequeue.bits.rs1Data
+  lsu.request.bits.rs2Data := requestRegDequeue.bits.rs2Data
   lsu.request.bits.instructionInformation.nf := requestRegDequeue.bits.instruction(31, 29)
   lsu.request.bits.instructionInformation.mew := requestRegDequeue.bits.instruction(28)
   lsu.request.bits.instructionInformation.mop := requestRegDequeue.bits.instruction(27, 26)
@@ -1595,7 +1590,7 @@ class T1(val parameter: T1Parameter)
   lsu.maskInput.zip(lsu.maskSelect).foreach { case (data, index) =>
     data :=  cutUInt(v0.asUInt, parameter.maskGroupWidth)(index)
   }
-  lsu.csrInterface := requestReg.bits.csr
+  lsu.csrInterface := requestRegCSR
   lsu.csrInterface.vl := evlForLsu
   lsu.writeReadyForLsu := VecInit(laneVec.map(_.writeReadyForLsu)).asUInt.andR
   lsu.vrfReadyToStore := VecInit(laneVec.map(_.vrfReadyToStore)).asUInt.andR
@@ -1681,10 +1676,13 @@ class T1(val parameter: T1Parameter)
         // Ensuring commit order
         inst.record.instructionIndex === responseCounter
     })
-    io.response.valid := slotCommit.asUInt.orR
-    io.response.bits.data := Mux(ffoType, ffoIndexReg.bits, dataResult.bits)
-    io.response.bits.vxsat := DontCare
-    io.response.bits.mem := (slotCommit.asUInt & VecInit(slots.map(_.record.isLoadStore)).asUInt).orR
+    retire := slotCommit.asUInt.orR
+    io.retire.rd.bits.rdData := Mux(ffoType, ffoIndexReg.bits, dataResult.bits)
+    // TODO: csr retire.
+    io.retire.csr.bits.vxsat := DontCare
+    io.retire.csr.bits.fflag := DontCare
+    io.retire.csr.valid := false.B
+    io.retire.mem.valid := (slotCommit.asUInt & VecInit(slots.map(_.record.isLoadStore)).asUInt).orR
     lastSlotCommit := slotCommit.last
   }
 
@@ -1716,6 +1714,7 @@ class T1(val parameter: T1Parameter)
   probeWire.instructionCounter := instructionCounter
   probeWire.instructionIssue := requestRegDequeue.fire
   probeWire.issueTag := requestReg.bits.instructionIndex
+  probeWire.retireValid := retire
   // maskUnitWrite maskUnitWriteReady
   probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
   probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex