diff --git a/elaborator/src/PerfMonitor.scala b/elaborator/src/PerfMonitor.scala index f3c1d77858..31e2da6a17 100644 --- a/elaborator/src/PerfMonitor.scala +++ b/elaborator/src/PerfMonitor.scala @@ -95,31 +95,32 @@ class VMonitor(param: VParam) extends PerfMonitor { * Monitor signals in [[v.SimpleAccessUnit]] */ class OtherUnitMonitor extends PerfMonitor { - val lsuRequestIsValid = dpiIn("SimpleAccessUnitLSURequestIsValid", Input(Bool())) - - val vrfReadDataPortsIsReady = dpiIn("SimpleAccessUnitVRFReadDataPortsIsReady", Input(Bool())) - val vrfReadDataPortsIsValid = dpiIn("SimpleAccessUnitVRFReadDataPortsIsValid", Input(Bool())) - - val maskSelectIsValid = dpiIn("SimpleAccessUnitMaskSelectIsValid", Input(Bool())) - - val vrfWritePortIsReady = dpiIn("SimpleAccessUnitVRFWritePortIsReady", Input(Bool())) - val vrfWritePortIsValid = dpiIn("SimpleAccessUnitVRFWritePortIsValid", Input(Bool())) + val lsuRequestIsValid = dpiIn("lsuRequestIsValid", Input(Bool())) - val targetLane = dpiIn("SimpleAccessUnitStatusTargetLane", Input(UInt(32.W))) - val idle = dpiIn("SimpleAccessUnitIsIdle", Input(Bool())) + val s0EnqueueValid = dpiIn("s0EnqueueValid", Input(Bool())) + val stateIsRequest = dpiIn("stateIsRequest", Input(Bool())) + val maskCheck = dpiIn("maskCheck", Input(Bool())) + val indexCheck = dpiIn("indexCheck", Input(Bool())) + val fofCheck = dpiIn("fofCheck", Input(Bool())) - val s0Fire = dpiIn("SimpleAccessUnitS0Fire", Input(Bool())) - val s1Fire = dpiIn("SimpleAccessUnitS1Fire", Input(Bool())) - val s2Fire = dpiIn("SimpleAccessUnitS2Fire", Input(Bool())) -} + val s0Fire = dpiIn("s0Fire", Input(Bool())) + val s1Fire = dpiIn("s1Fire", Input(Bool())) + val s2Fire = dpiIn("s2Fire", Input(Bool())) -class OtherUnitAccessTileLinkMonitor extends ValidMonitor with ReadyMonitor + val tlPortAIsReady = dpiIn("tlPortAIsReady", Input(Bool())) + val tlPortAIsValid = dpiIn("tlPortAIsValid", Input(Bool())) + val s1Valid = dpiIn("s1Valid", Input(Bool())) + val sourceFree = dpiIn("sourceFree", Input(Bool())) -class OtherUnitTileLinkAckMonitor extends ValidMonitor with ReadyMonitor + val tlPortDIsValid = dpiIn("tlPortDIsValid", Input(Bool())) + val tlPortDIsReady = dpiIn("tlPortDIsReady", Input(Bool())) -class OtherUnitOffsetReadResultMonitor extends IndexedPerfMonitor with ValidMonitor + // Can't use 'VRF' here cuz it will be parsed as 'v_r_f' at DPI side + val vrfWritePortIsReady = dpiIn("VrfWritePortIsReady", Input(Bool())) + val vrfWritePortIsValid = dpiIn("VrfWritePortIsValid", Input(Bool())) -class OtherUnitIndexedInsnOffsetsIsValidMonitor extends IndexedPerfMonitor with ValidMonitor + val stateValue = dpiIn("stateValue", Input(UInt(32.W))) +} // End of SimpleAccessUnit monitors definition class LaneReadBusPortMonitor extends IndexedPerfMonitor { diff --git a/elaborator/src/TestBench.scala b/elaborator/src/TestBench.scala index d47f99003e..afa1dc4a16 100644 --- a/elaborator/src/TestBench.scala +++ b/elaborator/src/TestBench.scala @@ -124,40 +124,23 @@ class TestBench(generator: SerializableModuleGenerator[V, VParameter]) extends R val otherUnitMonitor = Module(new OtherUnitMonitor) otherUnitMonitor.clock.ref := clock.asBool otherUnitMonitor.lsuRequestIsValid.ref := read(bore(dut.lsu.otherUnit.lsuRequestValidProbe)) - otherUnitMonitor.vrfReadDataPortsIsReady.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsValidProbe)) - otherUnitMonitor.vrfReadDataPortsIsValid.ref := read(bore(dut.lsu.otherUnit.vrfReadDataPortsReadyProbe)) - otherUnitMonitor.maskSelectIsValid.ref := read(bore(dut.lsu.otherUnit.maskSelectValidProbe)) - otherUnitMonitor.vrfWritePortIsReady.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsReadyProbe)) - otherUnitMonitor.vrfWritePortIsValid.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsValidProbe)) - otherUnitMonitor.targetLane.ref := read(bore(dut.lsu.otherUnit.targetLaneProbe)) - otherUnitMonitor.idle.ref := read(bore(dut.lsu.otherUnit.statusIdleProbe)) + otherUnitMonitor.s0EnqueueValid.ref := read(bore(dut.lsu.otherUnit.s0EnqueueValidProbe)) + otherUnitMonitor.stateIsRequest.ref := read(bore(dut.lsu.otherUnit.stateIsRequestProbe)) + otherUnitMonitor.maskCheck.ref := read(bore(dut.lsu.otherUnit.maskCheckProbe)) + otherUnitMonitor.indexCheck.ref := read(bore(dut.lsu.otherUnit.indexCheckProbe)) + otherUnitMonitor.fofCheck.ref := read(bore(dut.lsu.otherUnit.fofCheckProbe)) otherUnitMonitor.s0Fire.ref := read(bore(dut.lsu.otherUnit.s0FireProbe)) otherUnitMonitor.s1Fire.ref := read(bore(dut.lsu.otherUnit.s1FireProbe)) otherUnitMonitor.s2Fire.ref := read(bore(dut.lsu.otherUnit.s2FireProbe)) - - val otherUnitAccessTileLinkMonitor = Module(new OtherUnitAccessTileLinkMonitor) - otherUnitAccessTileLinkMonitor.clock.ref := clock.asBool - otherUnitAccessTileLinkMonitor.isValid.ref := read(bore(dut.lsu.otherUnit.accessTileLinkValidProbe)) - otherUnitAccessTileLinkMonitor.isReady.ref := read(bore(dut.lsu.otherUnit.accessTileLinkReadyProbe)) - - val otherUnitTileLinkAckMonitor = Module(new OtherUnitTileLinkAckMonitor) - otherUnitTileLinkAckMonitor.clock.ref := clock.asBool - otherUnitTileLinkAckMonitor.isValid.ref := read(bore(dut.lsu.otherUnit.tileLinkAckValidProbe)) - otherUnitTileLinkAckMonitor.isReady.ref := read(bore(dut.lsu.otherUnit.tileLinkAckReadyProbe)) - - dut.lsu.otherUnit.offsetReadResultValidProbe.zipWithIndex.foreach({ case(probe, i) => - val monitor = Module(new OtherUnitOffsetReadResultMonitor) - monitor.clock.ref := clock.asBool - monitor.index.ref := i.U - monitor.isValid.ref := read(bore(probe)) - }) - - dut.lsu.otherUnit.indexedInsturctionOffsetsIsValidProbe.zipWithIndex.foreach({ case(probe, i) => - val monitor = Module(new OtherUnitIndexedInsnOffsetsIsValidMonitor) - monitor.clock.ref := clock.asBool - monitor.index.ref := i.U - monitor.isValid.ref := read(bore(probe)) - }) + otherUnitMonitor.tlPortAIsReady.ref := read(bore(dut.lsu.otherUnit.tlPortAReadyProbe)) + otherUnitMonitor.tlPortAIsValid.ref := read(bore(dut.lsu.otherUnit.tlPortAValidProbe)) + otherUnitMonitor.s1Valid.ref := read(bore(dut.lsu.otherUnit.s1ValidProbe)) + otherUnitMonitor.sourceFree.ref := read(bore(dut.lsu.otherUnit.sourceFreeProbe)) + otherUnitMonitor.tlPortDIsReady.ref := read(bore(dut.lsu.otherUnit.tlPortDReadyProbe)) + otherUnitMonitor.tlPortDIsValid.ref := read(bore(dut.lsu.otherUnit.tlPortDValidProbe)) + otherUnitMonitor.vrfWritePortIsReady.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsReadyProbe)) + otherUnitMonitor.vrfWritePortIsValid.ref := read(bore(dut.lsu.otherUnit.vrfWritePortIsValidProbe)) + otherUnitMonitor.stateValue.ref := read(bore(dut.lsu.otherUnit.stateValueProbe)) // End of [[v.SimpleAccessUnit]] related probe connection dut.laneVec.zipWithIndex.foreach({ case (lane, i) => diff --git a/emulator/src/dpi.cc b/emulator/src/dpi.cc index 9640959239..113ab31b64 100644 --- a/emulator/src/dpi.cc +++ b/emulator/src/dpi.cc @@ -307,151 +307,75 @@ void v_monitor(svLogic requestValid, svLogic requestReady, svLogic isLastInst3) { TRY({ Log("V") - .with("request", json{ - { "valid", (bool)requestValid }, - { "ready", (bool)requestReady }, - }) - .with("request_reg_valid", (bool)requestRegValid) - .with("request_reg_dequeue", json { - { "valid", (bool)requestRegDequeueValid }, - { "ready", (bool)requestRegDequeueReady }, - }) - .with("execution_ready", (bool)executionReady) - .with("slot_ready", (bool)slotReady) - .with("wait_for_gather", (bool)waitForGather) - .with("instrution_RAW_ready", (bool)instructionRawReady) - .with("response_valid", (bool)responseValid) - .with("slots", std::vector{ - json { { "s_mask_unit_exectued", (bool)sMaskUnitExecuted0 }, { "w_last", (bool)wLast0 }, { "is_last_instruction", (bool)isLastInst0 } }, - json { { "s_mask_unit_exectued", (bool)sMaskUnitExecuted1 }, { "w_last", (bool)wLast1 }, { "is_last_instruction", (bool)isLastInst1 } }, - json { { "s_mask_unit_exectued", (bool)sMaskUnitExecuted2 }, { "w_last", (bool)wLast2 }, { "is_last_instruction", (bool)isLastInst2 } }, - json { { "s_mask_unit_exectued", (bool)sMaskUnitExecuted3 }, { "w_last", (bool)wLast3 }, { "is_last_instruction", (bool)isLastInst3 } }, - }) - .info(); - }); -} - -[[maybe_unused]] void other_unit_monitor( - const svBit lsu_request_is_valid, const svBit vrf_read_data_port_is_ready, - const svBit vrf_read_data_port_is_valid, const svBit mask_select_is_valid, - const svBit vrf_write_port_is_ready, const svBit vrf_write_port_is_valid, - const svBitVecVal *targetLane, const svBit idle, const svBit s0_fire, - const svBit s1_fire, const svBit s2_fire) { - TRY({ - Log("OtherUnit") - .with("lsu_request_is_valid", (bool)lsu_request_is_valid) - .with("vrf_read_data_port", - json{{"is_ready", (bool)vrf_read_data_port_is_ready}, - {"is_valid", (bool)vrf_read_data_port_is_valid}}) - .with("vrf_write_port", - json{{"is_ready", (bool)vrf_write_port_is_ready}, - {"is_valid", (bool)vrf_write_port_is_valid}}) - .with("mask_select_is_valid", (bool)mask_select_is_valid) - .with("status", - json{ - {"target_lane", (int)(*targetLane)}, - {"is_idle", (bool)idle}, - }) - .with("s0_fire", (bool)s0_fire) - .with("s1_fire", (bool)s1_fire) - .with("s2_fire", (bool)s2_fire) - .info(); - }) -} - -[[maybe_unused]] void -other_unit_access_tile_link_monitor(const svBit is_valid, - const svBit is_ready) { - TRY({ - Log("OtherUnit") - .with("AccessTileLink", - json{ - {"is_valid", (bool)is_valid}, - {"is_ready", (bool)is_ready}, - }) - .info("Receive access tile link signal"); - }) -} - -[[maybe_unused]] void other_unit_tile_link_ack_monitor(const svBit is_valid, - const svBit is_ready) { - TRY({ - Log("OtherUnit") - .with("TileLinkAck", + .with("request", json{ - {"is_valid", (bool)is_valid}, - {"is_ready", (bool)is_ready}, + {"valid", (bool)requestValid}, + {"ready", (bool)requestReady}, }) - .info("Receive tile link ack signal"); - }) -} - -[[maybe_unused]] void -other_unit_offset_read_result_monitor(const svBitVecVal *index, - const svBit is_valid) { - TRY({ - Log("OtherUnit") - .with("index", (int)(*index)) - .with("is_valid", (bool)is_valid) - .info("receive offset read result signal"); - }) -} - -[[maybe_unused]] void -other_unit_indexed_insn_offsets_is_valid_monitor(const svBitVecVal *index, - const svBit is_valid) { - TRY({ - Log("OtherUnit") - .with("index", (int)(*index)) - .with("is_valid", (bool)is_valid) - .info("receive indexed instruction offset signal"); - }) -} - -[[maybe_unused]] void store_unit_monitor(const svBit vrf_ready_to_store) { - TRY({ - Log("StoreUnit") - .with("vrf_ready_to_store", (bool)vrf_ready_to_store) - .info(); - }) -} - -[[maybe_unused]] void store_unit_aligned_dequeue_monitor(const svBit is_valid, - const svBit is_ready) { - TRY({ - Log("StoreUnit") - .with("aligned_dequeue", + .with("request_reg_valid", (bool)requestRegValid) + .with("request_reg_dequeue", json{ - {"is_valid", (bool)is_valid}, - {"is_ready", (bool)is_ready}, + {"valid", (bool)requestRegDequeueValid}, + {"ready", (bool)requestRegDequeueReady}, }) - .info(); - }) -} - -[[maybe_unused]] void store_unit_tl_port_a_monitor(const svBitVecVal *index, - svLogic valid, - svLogic ready) { - TRY({ - Log("StoreUnit") - .with("TLPortA", - json{ - {"index", (int)(*index)}, - {"is_valid", (bool)valid}, - {"is_ready", (bool)ready}, + .with("execution_ready", (bool)executionReady) + .with("slot_ready", (bool)slotReady) + .with("wait_for_gather", (bool)waitForGather) + .with("instrution_RAW_ready", (bool)instructionRawReady) + .with("response_valid", (bool)responseValid) + .with("slots", + std::vector{ + json{{"s_mask_unit_exectued", (bool)sMaskUnitExecuted0}, + {"w_last", (bool)wLast0}, + {"is_last_instruction", (bool)isLastInst0}}, + json{{"s_mask_unit_exectued", (bool)sMaskUnitExecuted1}, + {"w_last", (bool)wLast1}, + {"is_last_instruction", (bool)isLastInst1}}, + json{{"s_mask_unit_exectued", (bool)sMaskUnitExecuted2}, + {"w_last", (bool)wLast2}, + {"is_last_instruction", (bool)isLastInst2}}, + json{{"s_mask_unit_exectued", (bool)sMaskUnitExecuted3}, + {"w_last", (bool)wLast3}, + {"is_last_instruction", (bool)isLastInst3}}, }) .info(); - }) + }); } -[[maybe_unused]] void -store_unit_vrf_read_data_port_monitor(const svBitVecVal *index, svLogic valid, - svLogic ready) { +void other_unit_monitor(svLogic lsuRequestIsValid, svLogic s0EnqueueValid, + svLogic stateIsRequest, svLogic maskCheck, + svLogic indexCheck, svLogic fofCheck, svLogic s0Fire, + svLogic s1Fire, svLogic s2Fire, svLogic tlPortAIsReady, + svLogic tlPortAIsValid, svLogic s1Valid, + svLogic sourceFree, svLogic tlPortDIsValid, + svLogic tlPortDIsReady, svLogic VrfWritePortIsReady, + svLogic VrfWritePortIsValid, + const svBitVecVal *stateValue) { TRY({ - Log("StoreUnitVrfReadDataPortReadyMonitor") - .with("index", (int)(*index)) - .with("is_valid", (bool)valid) - .with("is_ready", (bool)ready) + Log("OtherUnit") + .with("lsu_request_is_valid", (bool)lsuRequestIsValid) + .with("s0_enqueue_valid", (bool)s0EnqueueValid) + .with("state_is_request", (bool)stateIsRequest) + .with("mask_check", (bool)maskCheck) + .with("index_check", (bool)indexCheck) + .with("fof_check", (bool)fofCheck) + .with("s0_fire", (bool)s0Fire) + .with("s1_fire", (bool)s1Fire) + .with("s2_fire", (bool)s2Fire) + .with("tl_port_a", json { + { "valid", (bool)tlPortAIsValid }, + { "ready", (bool)tlPortAIsReady } + }) + .with("s1_valid", (bool)s1Valid) + .with("source_free", (bool)sourceFree) + .with("tl_port_d", json { + { "valid", (bool)tlPortDIsValid }, + { "ready", (bool)tlPortDIsReady } + }) + .with("vrf_write_port", json { + { "valid", (bool)VrfWritePortIsValid }, + { "ready", (bool)VrfWritePortIsReady } + }) .info(); }) } diff --git a/v/src/lsu/SimpleAccessUnit.scala b/v/src/lsu/SimpleAccessUnit.scala index a14f74c54f..77d3be41e2 100644 --- a/v/src/lsu/SimpleAccessUnit.scala +++ b/v/src/lsu/SimpleAccessUnit.scala @@ -1007,50 +1007,45 @@ class SimpleAccessUnit(param: MSHRParam) extends Module with LSUPublic { val lsuRequestValidProbe = IO(Output(Probe(Bool()))) define(lsuRequestValidProbe, ProbeValue(lsuRequest.valid)) - val vrfReadDataPortsValidProbe = IO(Output(Probe(Bool()))) - val vrfReadDataPortsReadyProbe = IO(Output(Probe(Bool()))) - define(vrfReadDataPortsValidProbe, ProbeValue(vrfReadDataPorts.valid)) - define(vrfReadDataPortsReadyProbe, ProbeValue(vrfReadDataPorts.ready)) - - val offsetReadResultValidProbe: Seq[Bool] = offsetReadResult.map(result => { - val probe = IO(Output(Probe(Bool()))) - define(probe, ProbeValue(result.valid)) - probe - }) - - val maskSelectValidProbe: Bool = IO(Output(Probe(Bool()))) - define(maskSelectValidProbe, ProbeValue(maskSelect.valid)) - - val vrfWritePortIsValidProbe: Bool = IO(Output(Probe(Bool()))) - define(vrfWritePortIsValidProbe, ProbeValue(vrfWritePort.valid)) - val vrfWritePortIsReadyProbe: Bool = IO(Output(Probe(Bool()))) - define(vrfWritePortIsReadyProbe, ProbeValue(vrfWritePort.ready)) - - val targetLaneProbe: UInt = IO(Output(Probe(chiselTypeOf(status.targetLane)))) - define(targetLaneProbe, ProbeValue(status.targetLane)) - val statusIdleProbe: Bool = IO(Output(Probe(Bool()))) - define(statusIdleProbe, ProbeValue(status.idle)) + val s0EnqueueValidProbe = IO(Output(Probe(Bool()))) + define(s0EnqueueValidProbe, ProbeValue(s0EnqueueValid)) + val stateIsRequestProbe = IO(Output(Probe(Bool()))) + define(stateIsRequestProbe, ProbeValue(stateIsRequest)) + val maskCheckProbe = IO(Output(Probe(Bool()))) + define(maskCheckProbe, ProbeValue(maskCheck)) + val indexCheckProbe = IO(Output(Probe(Bool()))) + define(indexCheckProbe, ProbeValue(indexCheck)) + val fofCheckProbe = IO(Output(Probe(Bool()))) + define(fofCheckProbe, ProbeValue(fofCheck)) val s0FireProbe: Bool = IO(Output(Probe(chiselTypeOf(s0Fire)))) define(s0FireProbe, ProbeValue(s0Fire)) + val s1FireProbe: Bool = IO(Output(Probe(chiselTypeOf(s1Fire)))) define(s1FireProbe, ProbeValue(s1Fire)) + + val tlPortAReadyProbe = IO(Output(Probe(Bool()))) + define(tlPortAReadyProbe, ProbeValue(tlPort.a.ready)) + val tlPortAValidProbe = IO(Output(Probe(Bool()))) + define(tlPortAValidProbe, ProbeValue(tlPort.a.valid)) + val s1ValidProbe = IO(Output(Probe(Bool()))) + define(s1ValidProbe, ProbeValue(s1Valid)) + val sourceFreeProbe = IO(Output(Probe(Bool()))) + define(sourceFreeProbe, ProbeValue(sourceFree)) + val s2FireProbe: Bool = IO(Output(Probe(chiselTypeOf(s2Fire)))) define(s2FireProbe, ProbeValue(s2Fire)) - val indexedInsturctionOffsetsIsValidProbe: IndexedSeq[Bool] = indexedInstructionOffsets.map(offset => { - val probe = IO(Output(Probe(Bool()))) - define(probe, ProbeValue(offset.valid)) - probe - }) - - val accessTileLinkValidProbe = IO(Output(Probe(Bool()))) - define(accessTileLinkValidProbe, ProbeValue(tlPort.a.valid)) - val accessTileLinkReadyProbe = IO(Output(Probe(Bool()))) - define(accessTileLinkReadyProbe, ProbeValue(tlPort.a.ready)) - - val tileLinkAckValidProbe = IO(Output(Probe(Bool()))) - define(tileLinkAckValidProbe, ProbeValue(tlPort.d.valid)) - val tileLinkAckReadyProbe = IO(Output(Probe(Bool()))) - define(tileLinkAckReadyProbe, ProbeValue(tlPort.d.ready)) + val tlPortDReadyProbe = IO(Output(Probe(Bool()))) + define(tlPortDReadyProbe, ProbeValue(tlPort.d.ready)) + val tlPortDValidProbe = IO(Output(Probe(Bool()))) + define(tlPortDValidProbe, ProbeValue(tlPort.d.valid)) + + val stateValueProbe: UInt = IO(Output(Probe(chiselTypeOf(state)))) + define(stateValueProbe, ProbeValue(state)) + + val vrfWritePortIsValidProbe: Bool = IO(Output(Probe(Bool()))) + define(vrfWritePortIsValidProbe, ProbeValue(vrfWritePort.valid)) + val vrfWritePortIsReadyProbe: Bool = IO(Output(Probe(Bool()))) + define(vrfWritePortIsReadyProbe, ProbeValue(vrfWritePort.ready)) }