diff --git a/common.sc b/common.sc
index 697a8cf3f..5a6e2350b 100644
--- a/common.sc
+++ b/common.sc
@@ -4,8 +4,7 @@
 import mill._
 import mill.scalalib._
 
-trait HasChisel
-  extends ScalaModule {
+trait HasChisel extends ScalaModule {
   // Define these for building chisel from source
   def chiselModule: Option[ScalaModule]
 
@@ -13,7 +12,9 @@ trait HasChisel
 
   def chiselPluginJar: T[Option[PathRef]]
 
-  override def scalacOptions = T(super.scalacOptions() ++ chiselPluginJar().map(path => s"-Xplugin:${path.path}") ++ Seq("-Ymacro-annotations"))
+  override def scalacOptions = T(
+    super.scalacOptions() ++ chiselPluginJar().map(path => s"-Xplugin:${path.path}") ++ Seq("-Ymacro-annotations")
+  )
 
   override def scalacPluginClasspath: T[Agg[PathRef]] = T(super.scalacPluginClasspath() ++ chiselPluginJar())
 
@@ -24,14 +25,16 @@ trait HasChisel
 
   def chiselPluginIvy: Option[Dep]
 
-  override def scalacPluginIvyDeps: T[Agg[Dep]] = T(super.scalacPluginIvyDeps() ++ chiselPluginIvy.map(Agg(_)).getOrElse(Agg.empty[Dep]))
+  override def scalacPluginIvyDeps: T[Agg[Dep]] = T(
+    super.scalacPluginIvyDeps() ++ chiselPluginIvy.map(Agg(_)).getOrElse(Agg.empty[Dep])
+  )
 }
 
 trait HasRVDecoderDB extends ScalaModule {
   def rvdecoderdbModule: ScalaModule
-  def riscvOpcodesPath: T[PathRef]
+  def riscvOpcodesPath:  T[PathRef]
   def moduleDeps = super.moduleDeps ++ Seq(rvdecoderdbModule)
-  def riscvOpcodesTar: T[PathRef] = T {
+  def riscvOpcodesTar:    T[PathRef]      = T {
     val tmpDir = os.temp.dir()
     os.makeDir(tmpDir / "unratified")
     os.walk(riscvOpcodesPath().path)
@@ -41,10 +44,12 @@ trait HasRVDecoderDB extends ScalaModule {
           f.baseName.startsWith("rv32_") ||
           f.baseName.startsWith("rv_") ||
           f.ext == "csv"
-      ).groupBy(_.segments.contains("unratified")).map {
-          case (true, fs) => fs.map(os.copy.into(_, tmpDir / "unratified"))
-          case (false, fs) => fs.map(os.copy.into(_, tmpDir))
-        }
+      )
+      .groupBy(_.segments.contains("unratified"))
+      .map {
+        case (true, fs)  => fs.map(os.copy.into(_, tmpDir / "unratified"))
+        case (false, fs) => fs.map(os.copy.into(_, tmpDir))
+      }
     os.proc("tar", "cf", T.dest / "riscv-opcodes.tar", ".").call(tmpDir)
     PathRef(T.dest)
   }
@@ -52,19 +57,15 @@ trait HasRVDecoderDB extends ScalaModule {
 }
 
 // Local definitions
-trait T1Module
-  extends ScalaModule
-    with HasChisel
-    with HasRVDecoderDB {
+trait T1Module extends ScalaModule with HasChisel with HasRVDecoderDB {
   def arithmeticModule: ScalaModule
-  def hardfloatModule: ScalaModule
-  def axi4Module: ScalaModule
-  def stdlibModule: ScalaModule
+  def hardfloatModule:  ScalaModule
+  def axi4Module:       ScalaModule
+  def stdlibModule:     ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(arithmeticModule, hardfloatModule, axi4Module, stdlibModule)
 }
 
-trait ConfigGenModule
-  extends ScalaModule {
+trait ConfigGenModule extends ScalaModule {
   def t1Module: ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(t1Module)
   def mainargsIvy: Dep
@@ -72,101 +73,91 @@ trait ConfigGenModule
 }
 
 // T1 forked version of RocketCore
-trait RocketModule
-  extends ScalaModule
-    with HasChisel
-    with HasRVDecoderDB {
+trait RocketModule extends ScalaModule with HasChisel with HasRVDecoderDB {
   def rocketchipModule: ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(rocketchipModule)
 }
 
 // The next generation of purely standalone Rocket Core w/ AXI/CHI.
-trait RocketVModule
-  extends ScalaModule
-    with HasChisel
-    with HasRVDecoderDB {
-  def axi4Module: ScalaModule
+trait RocketVModule extends ScalaModule with HasChisel with HasRVDecoderDB {
+  def axi4Module:      ScalaModule
   def hardfloatModule: ScalaModule
-  def stdlibModule: ScalaModule
+  def stdlibModule:    ScalaModule
 
   def moduleDeps = super.moduleDeps ++ Seq(axi4Module, hardfloatModule, stdlibModule)
 }
 
 // Link T1 example: RocketV+T1
-trait T1RocketModule
-  extends ScalaModule
-    with HasChisel {
+trait T1RocketModule extends ScalaModule with HasChisel {
   def rocketModule: ScalaModule
-  def t1Module: ScalaModule
+  def t1Module:     ScalaModule
 
   def moduleDeps = super.moduleDeps ++ Seq(rocketModule, t1Module)
 }
 
-trait EmuHelperModule
-  extends ScalaModule
-    with HasChisel
+trait EmuHelperModule extends ScalaModule with HasChisel
 
-trait T1EmulatorModule
-  extends ScalaModule
-    with HasChisel {
+trait T1EmulatorModule extends ScalaModule with HasChisel {
   def t1Module: ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(t1Module)
 }
 
-trait T1RocketEmulatorModule
-  extends ScalaModule
-    with HasChisel {
+trait T1RocketEmulatorModule extends ScalaModule with HasChisel {
   def t1rocketModule: ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(t1rocketModule)
 }
 
-trait ElaboratorModule
-  extends ScalaModule
-    with HasChisel {
-  def generators: Seq[ScalaModule]
+trait ElaboratorModule extends ScalaModule with HasChisel {
+  def generators:            Seq[ScalaModule]
   def panamaconverterModule: ScalaModule
-  def circtInstallPath: T[PathRef]
+  def circtInstallPath:      T[PathRef]
   override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule) ++ generators
   def mainargsIvy: Dep
-  override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
+  override def ivyDeps      = T(super.ivyDeps() ++ Seq(mainargsIvy))
   override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
   override def forkArgs: T[Seq[String]] = T(
-    super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
+    super.forkArgs() ++ Seq(
+      "--enable-native-access=ALL-UNNAMED",
+      "--enable-preview",
+      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
+    )
   )
 }
 
-trait OMReaderLibModule
-  extends ScalaModule
-    with HasChisel {
+trait OMReaderLibModule extends ScalaModule with HasChisel {
   def panamaconverterModule: ScalaModule
-  def circtInstallPath: T[PathRef]
+  def circtInstallPath:      T[PathRef]
   override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule)
   def mainargsIvy: Dep
-  override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
+  override def ivyDeps      = T(super.ivyDeps() ++ Seq(mainargsIvy))
   override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
   override def forkArgs: T[Seq[String]] = T(
-    super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
+    super.forkArgs() ++ Seq(
+      "--enable-native-access=ALL-UNNAMED",
+      "--enable-preview",
+      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
+    )
   )
 }
 
-trait OMReaderModule
-  extends ScalaModule
-    with HasChisel {
+trait OMReaderModule extends ScalaModule with HasChisel {
   def panamaconverterModule: ScalaModule
-  def omreaderlibModule: ScalaModule
-  def circtInstallPath: T[PathRef]
+  def omreaderlibModule:     ScalaModule
+  def circtInstallPath:      T[PathRef]
   override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule, omreaderlibModule)
   def mainargsIvy: Dep
-  override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
+  override def ivyDeps      = T(super.ivyDeps() ++ Seq(mainargsIvy))
   override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
   override def forkArgs: T[Seq[String]] = T(
-    super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
+    super.forkArgs() ++ Seq(
+      "--enable-native-access=ALL-UNNAMED",
+      "--enable-preview",
+      s"-Djava.library.path=${circtInstallPath().path / "lib"}"
+    )
   )
 }
 
-trait RocketEmulatorModule
-  extends ScalaModule
-    with HasChisel {
+trait RocketEmulatorModule extends ScalaModule with HasChisel {
   def rocketVModule: ScalaModule
   def moduleDeps = super.moduleDeps ++ Seq(rocketVModule)
 }