From ed7bf72111b4590e07473340324e05b41b16642e Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 31 Jul 2024 13:31:52 +0800 Subject: [PATCH] [ipemu] debug for xprop --- ipemu/src/TestBench.scala | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index 9fb627c335..21c3ad75a3 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -120,16 +120,13 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) val issue = WireDefault(0.U.asTypeOf(new Issue)) val fence = RegInit(false.B) val outstanding = RegInit(0.U(4.W)) - val doIssue: Bool = dut.io.issue.ready && !fence && !reset - outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid - // used to gate Xprop when DPI hasn't issued yet. - val didIssue = RegInit(false.B) - didIssue := doIssue || didIssue + val hasBeenReset = RegNext(true.B, false.B) + val doIssue: Bool = dut.io.issue.ready && !fence && hasBeenReset + outstanding := outstanding + (RegNext(doIssue) && (issue.meta === 1.U)) - dut.io.issue.valid // TODO: refactor driver to spawn 3 scoreboards for record different retirement. val t1Probe = probe.read(dut.io.t1Probe) - fence := Mux(doIssue, issue.meta === 2.U, fence && !t1Probe.retireValid && !(outstanding === 0.U)) - - issue := Mux(didIssue || doIssue, + fence := Mux(RegNext(doIssue), issue.meta === 2.U, fence && !t1Probe.retireValid && !(outstanding === 0.U)) + issue := Mux(doIssue, RawClockedNonVoidFunctionCall("issue_vector_instruction", new Issue)( clock, doIssue,