From df115fe6ee55b29d520adbfaf2aa69fa23d0c178 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Sun, 25 Aug 2024 17:12:34 +0800 Subject: [PATCH] [test] pipe isVector for float write(1 cycle for IntToFP). --- t1rocketemu/src/TestBench.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index 884b6ce14..b5c8b02ed 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -198,10 +198,11 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil fpuParameter.fLen, fpuParameter.minFLen ))) + val isVectorForLLWrite = RegNext(rocketProbe.isVector, false.B) fpToIEEE.io.clock := clock fpToIEEE.io.reset := reset - fpToIEEE.io.in.valid := fpu.pipeWrite.rfWen || (fpu.loadOrVectorWrite.rfWen && !rocketProbe.isVector) + fpToIEEE.io.in.valid := fpu.pipeWrite.rfWen || (fpu.loadOrVectorWrite.rfWen && !isVectorForLLWrite) fpToIEEE.io.in.bits.data := Mux(fpu.pipeWrite.rfWen, fpu.pipeWrite.rfWdata, fpu.loadOrVectorWrite.rfWdata) fpToIEEE.io.in.bits.typeTag := Mux(fpu.pipeWrite.rfWen, fpu.pipeWrite.rfWtypeTag, fpu.loadOrVectorWrite.rfWtypeTag)