From dda920b75237bfd7662816024a9e35f787a20a34 Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Sun, 13 Oct 2024 21:29:08 +0800 Subject: [PATCH] [ipemu] filter 64-bit width instructions in t1 emu coverage flow --- t1emu/src/TestBench.scala | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/t1emu/src/TestBench.scala b/t1emu/src/TestBench.scala index 1896f6f8c..698469077 100644 --- a/t1emu/src/TestBench.scala +++ b/t1emu/src/TestBench.scala @@ -253,10 +253,10 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) RegInit(0.U.asTypeOf(Valid(UInt(16.W)))) } vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard)) - val instructionValid = + val instructionValid = (laneProbes.map(laneProbe => laneProbe.instructionValid ## laneProbe.instructionValid) :+ lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _) - val scoreboardEnq = + val scoreboardEnq = Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * generator.parameter.chainingSize).W)) vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) => val writeEnq: UInt = VecInit( @@ -285,7 +285,24 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) scoreboard.bits := 0.U } } - generator.parameter.decoderParam.allInstructions.map { instruction: Instruction => + // coverage + val unsupportedInstructions = Seq( + // format: off + "vfncvt_f_f_w", "vfncvt_f_x_w", "vfncvt_f_xu_w", "vfncvt_rod_f_f_w", "vfncvt_rtz_x_f_w", "vfncvt_rtz_xu_f_w", "vfncvt_x_f_w", "vfncvt_xu_f_w", + "vfslide1up_vf", "vfslide1down_vf", + "vfwadd_vf", "vfwadd_vv", "vfwadd_wf", "vfwadd_wv", + "vfwcvt_f_f_v", "vfwcvt_f_x_v", "vfwcvt_f_xu_v", "vfwcvt_rtz_x_f_v", "vfwcvt_rtz_xu_f_v", "vfwcvt_x_f_v", "vfwcvt_xu_f_v", + "vfwmacc_vf", "vfwmacc_vv", "vfwmsac_vf", "vfwmsac_vv", + "vfwmul_vf", "vfwmul_vv", "vfwnmacc_vf", "vfwnmacc_vv", + "vfwnmsac_vf", "vfwnmsac_vv", "vfwredosum_vs", "vfwredusum_vs", + "vfwsub_vf", "vfwsub_vv", "vfwsub_wf", "vfwsub_wv", "vl1re64_v", + "vl2re64_v", "vl4re64_v", "vl8re64_v", "vle64_v", "vle64ff_v", "vloxei64_v", "vlse64_v", "vluxei64_v", + "vmfle_vf", "vmfle_vv", "vse64_v", "vsext_vf8", "vsoxei64_v", "vsse64_v", "vsuxei64_v", "vzext_vf8" + // format: on + ) + generator.parameter.decoderParam.allInstructions.filter { instruction: Instruction => + !unsupportedInstructions.contains(instruction.name) + }.map { instruction: Instruction => val issueMatch = Sequence.BoolSequence(issue.instruction === BitPat("b" + instruction.encoding.toString)) CoverProperty(issueMatch, label = Some(s"t1_cover_issue_${instruction.name}")) }