diff --git a/t1/src/lsu/LoadUnit.scala b/t1/src/lsu/LoadUnit.scala
index 508b6fbbc8..ec2950c130 100644
--- a/t1/src/lsu/LoadUnit.scala
+++ b/t1/src/lsu/LoadUnit.scala
@@ -109,8 +109,8 @@ class LoadUnit(param: MSHRParam) extends StrideBase(param)  with LSUPublic {
 
   val alignedDequeueValid: Bool =
     unalignedCacheLine.valid &&
-      // 只有在base address 对齐的时候才需要推出最后一条访问的cache line
-      (dataValid || ((unalignedCacheLine.bits.index === cacheLineNumberReg) && baseAddressAlignedReg))
+      // 只有在 vlMisaligned || base address 对齐的时候才需要推出最后一条访问的cache line
+      (dataValid || ((unalignedCacheLine.bits.index === cacheLineNumberReg) && (vlMisalignedReg || baseAddressAlignedReg)))
   // update unalignedCacheLine
   when(unalignedEnqueueFire) {
     unalignedCacheLine.bits.data := nextData
diff --git a/t1/src/lsu/StrideBase.scala b/t1/src/lsu/StrideBase.scala
index ad2133ea12..6662c13949 100644
--- a/t1/src/lsu/StrideBase.scala
+++ b/t1/src/lsu/StrideBase.scala
@@ -173,12 +173,15 @@ abstract class StrideBase(param: MSHRParam) extends Module {
   val bytePerInstruction = ((nFiled * csrInterface.vl) << lsuRequest.bits.instructionInformation.eew).asUInt
 
   val baseAddressAligned: Bool = !lsuRequest.bits.rs1Data(param.cacheLineBits - 1, 0).orR
+  val vlMisaligned: Bool = bytePerInstruction(param.cacheLineBits - 1, 0).orR
 
   /** How many cache lines will be accessed by this instruction
    * nFiled * vl * (2 ** eew) / 32
    */
   val lastCacheLineIndex: UInt = (bytePerInstruction >> param.cacheLineBits).asUInt +
-    bytePerInstruction(param.cacheLineBits - 1, 0).orR - baseAddressAligned
+    vlMisaligned - baseAddressAligned
+
+  val vlMisalignedReg: Bool = RegEnable(vlMisaligned, false.B, lsuRequest.valid)
 
   val cacheLineNumberReg: UInt = RegEnable(lastCacheLineIndex, 0.U, lsuRequest.valid)
 }