diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index 5436960ae..615ef8f5d 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -47,7 +47,8 @@ class RocketProbe(param: RocketParameter) extends Bundle {
   val waitWen:        Bool                       = new Bool()
   val waitWaddr:      UInt                       = UInt(param.lgNXRegs.W)
   val isVectorCommit: Bool                       = Bool()
-  val isVectorWrite:  Bool                       = Bool()
+  val vectorWriteRD:  Bool                       = Bool()
+  val vectorWriteFD:  Bool                       = Bool()
   val idle:           Bool                       = Bool()
   // fpu score board
   val fpuScoreboard:  Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe)
@@ -1637,7 +1638,8 @@ class Rocket(val parameter: RocketParameter)
           wbRegValid && wbRegDecodeOutput(parameter.decoderParameter.vector) &&
           !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR)
         }.getOrElse(false.B)
-        probeWire.isVectorWrite  := t1RetireQueue.map(q => q.deq.fire).getOrElse(false.B)
+        probeWire.vectorWriteRD  := t1RetireQueue.map(q => q.deq.fire && !q.deq.bits.isFp).getOrElse(false.B)
+        probeWire.vectorWriteFD  := t1RetireQueue.map(q => q.deq.fire && q.deq.bits.isFp).getOrElse(false.B)
         probeWire.idle           := vectorEmpty
 
         probeWire.wbRegPc := wbRegPc
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
index 02a702057..032ae3c12 100644
--- a/t1rocketemu/src/TestBench.scala
+++ b/t1rocketemu/src/TestBench.scala
@@ -164,7 +164,7 @@ class TestBench(val parameter: T1RocketTileParameter)
   // output the probes
   // rocket reg write
   when(
-    rocketProbe.rfWen && !rocketProbe.isVectorWrite && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U)
+    rocketProbe.rfWen && !rocketProbe.vectorWriteRD && rocketProbe.rfWaddr =/= 0.U && !(rocketProbe.waitWen && rocketProbe.waitWaddr =/= 0.U)
   )(
     printf(
       cf"""{"event":"RegWrite","idx":${rocketProbe.rfWaddr},"data":"${rocketProbe.rfWdata}%x","cycle":${simulationTime}}\n"""
@@ -190,7 +190,7 @@ class TestBench(val parameter: T1RocketTileParameter)
           )
         )
       )
-      val isVectorForLLWrite = RegNext(rocketProbe.isVectorWrite, false.B)
+      val isVectorForLLWrite = RegNext(rocketProbe.vectorWriteFD, false.B)
 
       fpToIEEE.io.clock           := clock
       fpToIEEE.io.reset           := reset