diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index a7ab45e5b..091b50d97 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -298,23 +298,26 @@ case class T1Parameter(
 }
 
 class T1Probe(parameter: T1Parameter) extends Bundle {
-  val instructionCounter: UInt           = UInt(parameter.instructionIndexBits.W)
-  val instructionIssue:   Bool           = Bool()
-  val issueTag:           UInt           = UInt(parameter.instructionIndexBits.W)
-  val retireValid:        Bool           = Bool()
+  val instructionCounter: UInt                           = UInt(parameter.instructionIndexBits.W)
+  val instructionIssue:   Bool                           = Bool()
+  val issueTag:           UInt                           = UInt(parameter.instructionIndexBits.W)
+  val retireValid:        Bool                           = Bool()
+  // for profiler
+  val requestReg:         ValidIO[InstructionPipeBundle] = ValidIO(new InstructionPipeBundle(parameter))
+  val requestRegReady:    Bool                           = Bool()
   // write queue enq for mask unit
-  val writeQueueEnq:      ValidIO[UInt]  = Valid(UInt(parameter.instructionIndexBits.W))
-  val writeQueueEnqMask:  UInt           = UInt((parameter.datapathWidth / 8).W)
+  val writeQueueEnq:      ValidIO[UInt]                  = Valid(UInt(parameter.instructionIndexBits.W))
+  val writeQueueEnqMask:  UInt                           = UInt((parameter.datapathWidth / 8).W)
   // mask unit instruction valid
-  val instructionValid:   UInt           = UInt((parameter.chainingSize * 2).W)
+  val instructionValid:   UInt                           = UInt((parameter.chainingSize * 2).W)
   // instruction index for check rd
-  val responseCounter:    UInt           = UInt(parameter.instructionIndexBits.W)
+  val responseCounter:    UInt                           = UInt(parameter.instructionIndexBits.W)
   // probes
-  val lsuProbe:           LSUProbe       = new LSUProbe(parameter.lsuParameters)
-  val laneProbes:         Vec[LaneProbe] = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam))
-  val issue:              ValidIO[UInt]  = Valid(UInt(parameter.instructionIndexBits.W))
-  val retire:             ValidIO[UInt]  = Valid(UInt(parameter.xLen.W))
-  val idle:               Bool           = Bool()
+  val lsuProbe:           LSUProbe                       = new LSUProbe(parameter.lsuParameters)
+  val laneProbes:         Vec[LaneProbe]                 = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam))
+  val issue:              ValidIO[UInt]                  = Valid(UInt(parameter.instructionIndexBits.W))
+  val retire:             ValidIO[UInt]                  = Valid(UInt(parameter.xLen.W))
+  val idle:               Bool                           = Bool()
 }
 
 class T1Interface(parameter: T1Parameter) extends Record {
@@ -1751,6 +1754,8 @@ class T1(val parameter: T1Parameter)
     probeWire.instructionIssue    := requestRegDequeue.fire
     probeWire.issueTag            := requestReg.bits.instructionIndex
     probeWire.retireValid         := retire
+    probeWire.requestReg          := requestReg
+    probeWire.requestRegReady     := requestRegDequeue.ready
     // maskUnitWrite maskUnitWriteReady
     probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady
     probeWire.writeQueueEnq.bits  := maskUnitWrite.bits.instructionIndex
diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala
index 9391e8f2f..01c7dbc78 100644
--- a/t1rocket/src/T1RocketTile.scala
+++ b/t1rocket/src/T1RocketTile.scala
@@ -477,8 +477,8 @@ class T1RocketProbe(parameter: T1RocketTileParameter) extends Bundle {
   val fpuProbe:    Option[FPUProbe] = parameter.fpuParameter.map(param => Output(new FPUProbe(param)))
   val t1Probe:     T1Probe          = Output(new T1Probe(parameter.t1Parameter))
 
-  val t1IssueDeq:  DecoupledIO[T1Issue] = DecoupledIO(new T1Issue(parameter.xLen, parameter.vLen))
-  val t1Retire:    T1Retire         = Output(new T1Retire(parameter.xLen))
+  val t1IssueDeq: DecoupledIO[T1Issue] = DecoupledIO(new T1Issue(parameter.xLen, parameter.vLen))
+  val t1Retire:   T1Retire             = Output(new T1Retire(parameter.xLen))
 }
 
 class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {
@@ -624,6 +624,6 @@ class T1RocketTile(val parameter: T1RocketTileParameter)
     }
 
     probeWire.t1IssueDeq := t1.io.issue
-    probeWire.t1Retire := t1.io.retire
+    probeWire.t1Retire   := t1.io.retire
   }
 }
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
index c993f2704..2e78b38e3 100644
--- a/t1rocketemu/src/TestBench.scala
+++ b/t1rocketemu/src/TestBench.scala
@@ -339,13 +339,16 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
       val t1IssueEnqPc = WireInit(probe.rocketProbe.wbRegPc)
       val t1IssueEnq = WireInit(probe.rocketProbe.t1IssueEnq.get)
       val t1IssueDeq = WireInit(probe.t1IssueDeq)
+      val t1IssueRegDeq = WireInit(probe.t1Probe.requestReg)
+      val t1IssueRegDeqReady = WireInit(probe.t1Probe.requestRegReady)
       val t1Retire = WireInit(probe.t1Retire)
 
       dontTouch(this.clock)
       dontTouch(this.reset)
       dontTouch(t1IssueEnq)
-      dontTouch(t1IssueEnq)
       dontTouch(t1IssueDeq)
+      dontTouch(t1IssueRegDeq)
+      dontTouch(t1IssueRegDeqReady)
       dontTouch(t1Retire)
     })
     profData.probe := t1RocketProbe