diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index 106a26c4e0..1562b8a5ac 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -367,7 +367,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
   requestRegDequeue.valid := requestReg.valid
   // TODO: decode the 7 bits in LSB, to get the instruction type.
   //       we only need to use it to find if it's a load/store instruction.
-  decode.decodeInput := (request.bits.instruction >> 12) ## request.bits.instruction(6)
+  decode.decodeInput := request.bits.instruction
 
   /** alias to [[requestReg.bits.decodeResult]], it is commonly used. */
   val decodeResult: DecodeBundle = requestReg.bits.decodeResult
diff --git a/t1/src/VectorDecoder.scala b/t1/src/VectorDecoder.scala
index c3bcee6975..432e132a91 100644
--- a/t1/src/VectorDecoder.scala
+++ b/t1/src/VectorDecoder.scala
@@ -11,7 +11,7 @@ import org.chipsalliance.t1.rtl.decoder.Decoder
 @instantiable
 class VectorDecoder(fpuEnable: Boolean) extends Module {
   @public
-  val decodeInput: UInt = IO(Input(UInt(21.W)))
+  val decodeInput: UInt = IO(Input(UInt(32.W)))
   @public
   val decodeResult: DecodeBundle = IO(Output(new DecodeBundle(Decoder.all(fpuEnable))))