From ca2a4a9177e5d95215f6b5daec8bfb7dae6dae40 Mon Sep 17 00:00:00 2001
From: Clo91eaf <Clo91eaf@qq.com>
Date: Fri, 7 Jun 2024 15:16:08 +0800
Subject: [PATCH] [difftest] add [cycle] for check

[difftest] fix wrong lane number in peek vrf
---
 difftest/t1-simulator/src/difftest.rs                   | 3 ++-
 difftest/t1-simulator/src/difftest/spike.rs             | 6 +++---
 difftest/t1-simulator/src/difftest/spike/spike_event.rs | 8 ++++----
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/difftest/t1-simulator/src/difftest.rs b/difftest/t1-simulator/src/difftest.rs
index ca721a18a..7e59d8415 100644
--- a/difftest/t1-simulator/src/difftest.rs
+++ b/difftest/t1-simulator/src/difftest.rs
@@ -180,6 +180,7 @@ impl Difftest {
       }
       "inst" => {
         let data = event.parameter.data.unwrap();
+        let cycle = event.parameter.cycle.unwrap();
         // let vxsat = event.parameter.vxsat.unwrap();
         // let rd_valid = event.parameter.rd_valid.unwrap();
         // let rd = event.parameter.rd.unwrap();
@@ -187,7 +188,7 @@ impl Difftest {
 
         let se = self.spike.to_rtl_queue.back().unwrap();
         se.record_rd_write(data).unwrap();
-        se.check_is_ready_for_commit().unwrap();
+        se.check_is_ready_for_commit(cycle).unwrap();
 
         self.spike.to_rtl_queue.pop_back();
       }
diff --git a/difftest/t1-simulator/src/difftest/spike.rs b/difftest/t1-simulator/src/difftest/spike.rs
index 86f96a246..3994639c4 100644
--- a/difftest/t1-simulator/src/difftest/spike.rs
+++ b/difftest/t1-simulator/src/difftest/spike.rs
@@ -421,7 +421,7 @@ impl SpikeHandle {
     se.issue_idx = issue.idx as u8;
 
     info!(
-      "[{}] SpikePeekIssue: idx={}, pc = {:#x}, inst = {}",
+      "[{}] SpikePeekIssue: idx={}, pc={:#x}, inst={}",
       issue.cycle, issue.idx, se.pc, se.disasm
     );
 
@@ -449,7 +449,7 @@ impl SpikeHandle {
   pub fn peek_vrf_write_from_lsu(&mut self, vrf_write: VrfWriteEvent) -> anyhow::Result<()> {
     let cycle = vrf_write.cycle;
     let vlen_in_bytes = self.config.vlen / 8;
-    let lane_number = self.config.dlen / 8;
+    let lane_number = self.config.dlen / 32;
     let record_idx_base = (vrf_write.vd * vlen_in_bytes
       + (vrf_write.idx + lane_number * vrf_write.offset) * 4) as usize;
 
@@ -474,7 +474,7 @@ impl SpikeHandle {
   pub fn peek_vrf_write_from_lane(&mut self, vrf_write: VrfWriteEvent) -> anyhow::Result<()> {
     let cycle = vrf_write.cycle;
     let vlen_in_bytes = self.config.vlen / 8;
-    let lane_number = self.config.dlen / 8;
+    let lane_number = self.config.dlen / 32;
     let record_idx_base = (vrf_write.vd * vlen_in_bytes
       + (vrf_write.idx + lane_number * vrf_write.offset) * 4) as usize;
 
diff --git a/difftest/t1-simulator/src/difftest/spike/spike_event.rs b/difftest/t1-simulator/src/difftest/spike/spike_event.rs
index 6e92aeedc..5bc2c493e 100644
--- a/difftest/t1-simulator/src/difftest/spike/spike_event.rs
+++ b/difftest/t1-simulator/src/difftest/spike/spike_event.rs
@@ -355,12 +355,12 @@ impl SpikeEvent {
     Ok(())
   }
 
-  pub fn check_is_ready_for_commit(&self) -> anyhow::Result<()> {
+  pub fn check_is_ready_for_commit(&self, cycle: usize) -> anyhow::Result<()> {
     for (addr, record) in &self.mem_access_record.all_writes {
       assert_eq!(
         record.num_completed_writes,
         record.writes.len(),
-        "expect to write mem {addr:#x}, not executed when commit ({})",
+        "[{cycle}] expect to write mem {addr:#x}, not executed when commit ({})",
         format!("pc={:#x}, inst={}", self.pc, self.disasm)
       );
     }
@@ -368,14 +368,14 @@ impl SpikeEvent {
       assert_eq!(
         record.num_completed_reads,
         record.reads.len(),
-        "expect to read mem {addr:#x}, not executed when commit ({})",
+        "[{cycle}] expect to read mem {addr:#x}, not executed when commit ({})",
         format!("pc={:#x}, inst={}", self.pc, self.disasm)
       );
     }
     for (idx, record) in &self.vrf_access_record.all_writes {
       assert!(
         record.executed,
-        "expect to write vrf {idx}, not executed when commit ({})",
+        "[{cycle}] expect to write vrf {idx}, not executed when commit ({})",
         format!("pc={:#x}, inst={}", self.pc, self.disasm)
       );
     }