diff --git a/t1/src/decoder/attribute/adderUop.scala b/t1/src/decoder/attribute/adderUop.scala new file mode 100644 index 000000000..5f949d351 --- /dev/null +++ b/t1/src/decoder/attribute/adderUop.scala @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait AdderUOPType extends Uop +object T0 extends AdderUOPType +object T1 extends AdderUOPType +object T2 extends AdderUOPType +object T3 extends AdderUOPType +object T4 extends AdderUOPType +object T5 extends AdderUOPType +object T6 extends AdderUOPType +object T7 extends AdderUOPType +object T8 extends AdderUOPType +object T9 extends AdderUOPType +object T10 extends AdderUOPType +object T11 extends AdderUOPType +object T12 extends AdderUOPType +object T13 extends AdderUOPType +object T14 extends AdderUOPType +object T15 extends AdderUOPType +object DC extends AdderUOPType + +object AdderUOP { + def apply(t1DecodePattern: T1DecodePattern): AdderUOPType = { + Seq( + t0 _ -> T0, + t1 _ -> T1, + t2 _ -> T2, + t3 _ -> T3, + t4 _ -> T4, + t5 _ -> T5, + t6 _ -> T6, + t7 _ -> T7, + t8 _ -> T8, + t9 _ -> T9, + t10 _ -> T10, + t11 _ -> T11, + t12 _ -> T12, + t13 _ -> T13, + t14 _ -> T14, + t15 _ -> T15, + dc _ -> DC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vredsum.vs", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwredsum.vs", + "vwredsumu.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vrsub.vi", + "vrsub.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vsbc.vvm", + "vsbc.vxm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = false + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vredmax.vs", + "vredmaxu.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vredmin.vs", + "vredminu.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vsbc.vvm", + "vsbc.vxm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class AdderUOP(value: AdderUOPType) extends UopDecodeAttribute[AdderUOPType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/divUop.scala b/t1/src/decoder/attribute/divUop.scala new file mode 100644 index 000000000..afd7eb780 --- /dev/null +++ b/t1/src/decoder/attribute/divUop.scala @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait DivUOPType extends Uop +object T0 extends DivUOPType +object T1 extends DivUOPType +object T2 extends DivUOPType +object T3 extends DivUOPType +object T4 extends DivUOPType +object T5 extends DivUOPType +object T6 extends DivUOPType +object T7 extends DivUOPType +object T8 extends DivUOPType +object T9 extends DivUOPType +object T10 extends DivUOPType +object T11 extends DivUOPType +object T12 extends DivUOPType +object T13 extends DivUOPType +object T14 extends DivUOPType +object T15 extends DivUOPType +object DC extends DivUOPType + +object DivUOP { + def apply(t1DecodePattern: T1DecodePattern): DivUOPType = { + Seq( + t0 _ -> T0, + t1 _ -> T1, + t2 _ -> T2, + t3 _ -> T3, + t4 _ -> T4, + t5 _ -> T5, + t6 _ -> T6, + t7 _ -> T7, + t8 _ -> T8, + t9 _ -> T9, + t10 _ -> T10, + t11 _ -> T11, + t12 _ -> T12, + t13 _ -> T13, + t14 _ -> T14, + t15 _ -> T15, + dc _ -> DC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vfrdiv.vf", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = false + def t3(t1DecodePattern: T1DecodePattern): Boolean = false + def t4(t1DecodePattern: T1DecodePattern): Boolean = false + def t5(t1DecodePattern: T1DecodePattern): Boolean = false + def t6(t1DecodePattern: T1DecodePattern): Boolean = false + def t7(t1DecodePattern: T1DecodePattern): Boolean = false + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfdiv.vf", + "vfdiv.vv", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfsqrt.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfrdiv.vf", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = false + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class DivUOP(value: DivUOPType) extends UopDecodeAttribute[DivUOPType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/floatUop.scala b/t1/src/decoder/attribute/floatUop.scala new file mode 100644 index 000000000..fe27f0fd5 --- /dev/null +++ b/t1/src/decoder/attribute/floatUop.scala @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait FloatUopType extends Uop +object FUT0 extends FloatUopType +object FUT1 extends FloatUopType +object FUT2 extends FloatUopType +object FUT3 extends FloatUopType +object FUT4 extends FloatUopType +object FUT5 extends FloatUopType +object FUT6 extends FloatUopType +object FUT7 extends FloatUopType +object FUDC extends FloatUopType + +object FloatUop { + def apply(t1DecodePattern: T1DecodePattern): FloatUopType = { + Seq( + t0 _ -> FUT0, + dc _ -> FUDC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(t1(t1DecodePattern) + || t2(t1DecodePattern) + || t3(t1DecodePattern) + || t4(t1DecodePattern) + || t5(t1DecodePattern) + || t6(t1DecodePattern) + || t7(t1DecodePattern) + || t8(t1DecodePattern) + || t9(t1DecodePattern) + || t10(t1DecodePattern) + || t11(t1DecodePattern) + || t12(t1DecodePattern) + || t13(t1DecodePattern) + || t14(t1DecodePattern) + || t15(t1DecodePattern) + || dc(t1DecodePattern) + ) + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmsac.vf", + "vfmsac.vv", + "vfsgnj.vf", + "vfsgnj.vv", + "vmfeq.vf", + "vmfeq.vv", + "vfcvt.x.f.v", + "vfmax.vf", + "vfmax.vv", + "vfredmax.vs", + "vfcvt.rtz.xu.f.v", + "vfrsub.vf", + "vfcvt.rtz.x.f.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmsac.vf", + "vfnmsac.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vmflt.vf", + "vmflt.vv", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmacc.vf", + "vfnmacc.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vmfle.vf", + "vmfle.vv", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfclass.v", + "vfmadd.vf", + "vfmadd.vv", + "vmfgt.vf", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmsub.vf", + "vfmsub.vv", + "vmfge.vf", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmsub.vf", + "vfnmsub.vv", + "vfrec7.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfnmadd.vf", + "vfnmadd.vv", + "vfrsqrt7.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfadd.vf", + "vfadd.vv", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfmin.vf", + "vfmin.vv", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.xu.f.v", + "vfsub.vf", + "vfsub.vv", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.x.f.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmax.vf", + "vfmax.vv", + "vfredmax.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t13(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.rtz.xu.f.v", + "vfrsub.vf", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t14(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfcvt.rtz.x.f.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class FloatUop(value: FloatUopType) extends UopDecodeAttribute[FloatUopType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/fmaUOP.scala b/t1/src/decoder/attribute/fmaUOP.scala deleted file mode 100644 index 8cbbaad69..000000000 --- a/t1/src/decoder/attribute/fmaUOP.scala +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.rtl.decoder.attribute - -import org.chipsalliance.t1.rtl.decoder.T1DecodePattern - -trait FMAUopType extends Uop -object FMAT0 extends FMAUopType -object FMAT1 extends FMAUopType -object FMAT2 extends FMAUopType -object FMAT3 extends FMAUopType -object FMAT4 extends FMAUopType -object FMAT5 extends FMAUopType -object FMAT6 extends FMAUopType -object FMAT7 extends FMAUopType -object FMAT8 extends FMAUopType -object FMADC extends FMAUopType - -object fmaUOP { - def apply(t1DecodePattern: T1DecodePattern): fmaUOP = { - Seq( - t0 _ -> FMAT0, - t1 _ -> FMAT1, - t2 _ -> FMAT2, - t3 _ -> FMAT3, - t4 _ -> FMAT4, - t5 _ -> FMAT5, - t6 _ -> FMAT6, - t7 _ -> FMAT7, - t8 _ -> FMAT8, - dc _ -> FMADC, - ).collectFirst { - case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) - }.get - - } - def t0(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched: Seq[String] = Seq( - "vfadd", - "vfmacc", - "vfmul", - "vfredosum", - "vfredusum" - ) - allMatched.contains(t1DecodePattern.instruction.name) - } - def t1(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t2(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t3(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t4(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t5(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t6(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t7(t1DecodePattern: T1DecodePattern): Boolean = ??? - def t8(t1DecodePattern: T1DecodePattern): Boolean = ??? - def dc(t1DecodePattern: T1DecodePattern): Boolean = ??? -} - -case class fmaUOP(value: FMAUopType) extends UopDecodeAttribute[FMAUopType] { - override val description: String = "Some Thing" -} \ No newline at end of file diff --git a/t1/src/decoder/attribute/isTopuopsignextend.scala b/t1/src/decoder/attribute/isTopuopsignextend.scala deleted file mode 100644 index 5ab15d06a..000000000 --- a/t1/src/decoder/attribute/isTopuopsignextend.scala +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.rtl.decoder.attribute - -import org.chipsalliance.t1.rtl.decoder.T1DecodePattern - -object isTopuopsignextend { - def apply(t1DecodePattern: T1DecodePattern): isTopuopsignextend = - Seq( - y _ -> Y, - n _ -> N, - dc _ -> DC - ).collectFirst { - case (fn, tri) if fn(t1DecodePattern) => isTopuopsignextend(tri) - }.get - - def y(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = Seq( - "vsext.vf2", - "vsext.vf4", - "vsext.vf8", - ) - allMatched.contains(t1DecodePattern.instruction) - } - def n(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => - !(y(t1DecodePattern) || dc(t1DecodePattern)) - ) - allMatched.contains(t1DecodePattern.instruction) - } - - def dc(t1DecodePattern: T1DecodePattern): Boolean = false -} - -case class isTopuopsignextend(value: TriState) extends BooleanDecodeAttribute { - override val description: String = "signExtend" -} diff --git a/t1/src/decoder/attribute/isTopuopslid1.scala b/t1/src/decoder/attribute/isTopuopslid1.scala deleted file mode 100644 index 4aaee2bac..000000000 --- a/t1/src/decoder/attribute/isTopuopslid1.scala +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.rtl.decoder.attribute - -import org.chipsalliance.t1.rtl.decoder.T1DecodePattern - -object isTopuopslid1 { - def apply(t1DecodePattern: T1DecodePattern): isTopuopslid1 = - Seq( - y _ -> Y, - n _ -> N, - dc _ -> DC - ).collectFirst { - case (fn, tri) if fn(t1DecodePattern) => isTopuopslid1(tri) - }.get - - def y(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = Seq( - "vfslide1down.vf", - "vfslide1up.vf", - "vslide1down.vx", - "vslide1up.vx", - ) - allMatched.contains(t1DecodePattern.instruction) - } - def n(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => - !(y(t1DecodePattern) || dc(t1DecodePattern)) - ) - allMatched.contains(t1DecodePattern.instruction) - } - - def dc(t1DecodePattern: T1DecodePattern): Boolean = false -} - -case class isTopuopslid1(value: TriState) extends BooleanDecodeAttribute { - override val description: String = "slid1" -} diff --git a/t1/src/decoder/attribute/isTopuopup.scala b/t1/src/decoder/attribute/isTopuopup.scala deleted file mode 100644 index ee0405d26..000000000 --- a/t1/src/decoder/attribute/isTopuopup.scala +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.rtl.decoder.attribute - -import org.chipsalliance.t1.rtl.decoder.T1DecodePattern - -object isTopuopup { - def apply(t1DecodePattern: T1DecodePattern): isTopuopup = - Seq( - y _ -> Y, - n _ -> N, - dc _ -> DC - ).collectFirst { - case (fn, tri) if fn(t1DecodePattern) => isTopuopup(tri) - }.get - - def y(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = Seq( - "vfslide1up.vf", - "vslide1up.vx", - "vslideup.vi", - "vslideup.vx", - ) - allMatched.contains(t1DecodePattern.instruction) - } - def n(t1DecodePattern: T1DecodePattern): Boolean = { - val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => - !(y(t1DecodePattern) || dc(t1DecodePattern)) - ) - allMatched.contains(t1DecodePattern.instruction) - } - - def dc(t1DecodePattern: T1DecodePattern): Boolean = false -} - -case class isTopuopup(value: TriState) extends BooleanDecodeAttribute { - override val description: String = "up" -} diff --git a/t1/src/decoder/attribute/logicUop.scala b/t1/src/decoder/attribute/logicUop.scala new file mode 100644 index 000000000..9d920dc95 --- /dev/null +++ b/t1/src/decoder/attribute/logicUop.scala @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait LogicUopType extends Uop +object FUT0 extends LogicUopType +object FUT1 extends LogicUopType +object FUT2 extends LogicUopType +object FUT3 extends LogicUopType +object FUT4 extends LogicUopType +object FUT5 extends LogicUopType +object FUT6 extends LogicUopType +object FUT7 extends LogicUopType +object FUDC extends LogicUopType + +object LogicUop { + def apply(t1DecodePattern: T1DecodePattern): LogicUopType = { + Seq( + t0 _ -> FUT0, + dc _ -> FUDC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vand.vi", + "vand.vv", + "vand.vx", + "vmand.mm", + "vredand.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmor.mm", + "vor.vi", + "vor.vv", + "vor.vx", + "vredor.vs", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmxor.mm", + "vredxor.vs", + "vxor.vi", + "vxor.vv", + "vxor.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = false + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmandn.mm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmorn.mm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmxnor.mm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = false + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmnand.mm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmnor.mm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = false + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = false + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class LogicUop(value: LogicUopType) extends UopDecodeAttribute[LogicUopType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/mulUop.scala b/t1/src/decoder/attribute/mulUop.scala new file mode 100644 index 000000000..2c408d5cf --- /dev/null +++ b/t1/src/decoder/attribute/mulUop.scala @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait MulUOPType extends Uop +object T0 extends MulUOPType +object T1 extends MulUOPType +object T2 extends MulUOPType +object T3 extends MulUOPType +object T4 extends MulUOPType +object T5 extends MulUOPType +object T6 extends MulUOPType +object T7 extends MulUOPType +object T8 extends MulUOPType +object T9 extends MulUOPType +object T10 extends MulUOPType +object T11 extends MulUOPType +object T12 extends MulUOPType +object T13 extends MulUOPType +object T14 extends MulUOPType +object T15 extends MulUOPType +object DC extends MulUOPType + +object MulUOP { + def apply(t1DecodePattern: T1DecodePattern): MulUOPType = { + Seq( + t0 _ -> T0, + t1 _ -> T1, + t2 _ -> T2, + t3 _ -> T3, + t4 _ -> T4, + t5 _ -> T5, + t6 _ -> T6, + t7 _ -> T7, + t8 _ -> T8, + t9 _ -> T9, + t10 _ -> T10, + t11 _ -> T11, + t12 _ -> T12, + t13 _ -> T13, + t14 _ -> T14, + t15 _ -> T15, + dc _ -> DC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmul.vv", + "vmul.vx", + "vsmul.vv", + "vsmul.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmadd.vv", + "vmadd.vx", + "vnmsub.vv", + "vnmsub.vx", + "vnmsac.vv", + "vnmsac.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = false + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = false + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmacc.vv", + "vmacc.vx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = false + def t7(t1DecodePattern: T1DecodePattern): Boolean = false + def t8(t1DecodePattern: T1DecodePattern): Boolean = false + def t9(t1DecodePattern: T1DecodePattern): Boolean = false + def t10(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnmsub.vv", + "vnmsub.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnmsac.vv", + "vnmsac.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class MulUOP(value: MulUOPType) extends UopDecodeAttribute[MulUOPType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/otherUop.scala b/t1/src/decoder/attribute/otherUop.scala new file mode 100644 index 000000000..653194256 --- /dev/null +++ b/t1/src/decoder/attribute/otherUop.scala @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait OtherUopType extends Uop +object FUT0 extends OtherUopType +object FUT1 extends OtherUopType +object FUT2 extends OtherUopType +object FUT3 extends OtherUopType +object FUT4 extends OtherUopType +object FUT5 extends OtherUopType +object FUT6 extends OtherUopType +object FUT7 extends OtherUopType +object FUDC extends OtherUopType + +object OtherUop { + def apply(t1DecodePattern: T1DecodePattern): OtherUopType = { + Seq( + t0 _ -> FUT0, + dc _ -> FUDC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfirst.m", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsbf.m", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsof.m", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vmsif.m", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmerge.vfm", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfmv.s.f", + "vmv.s.x", + "vmv.x.s", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t8(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcpop.m", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t9(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vid.v", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t10(t1DecodePattern: T1DecodePattern): Boolean = false + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = false + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class OtherUop(value: OtherUopType) extends UopDecodeAttribute[OtherUopType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/shiftUop.scala b/t1/src/decoder/attribute/shiftUop.scala new file mode 100644 index 000000000..f89b5b1e5 --- /dev/null +++ b/t1/src/decoder/attribute/shiftUop.scala @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait ShiftUopType extends Uop +object FUT0 extends ShiftUopType +object FUT1 extends ShiftUopType +object FUT2 extends ShiftUopType +object FUT3 extends ShiftUopType +object FUT4 extends ShiftUopType +object FUT5 extends ShiftUopType +object FUT6 extends ShiftUopType +object FUT7 extends ShiftUopType +object FUDC extends ShiftUopType + +object ShiftUop { + def apply(t1DecodePattern: T1DecodePattern): ShiftUopType = { + Seq( + t0 _ -> FUT0, + dc _ -> FUDC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsll.vi", + "vsll.vv", + "vsll.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t3(t1DecodePattern: T1DecodePattern): Boolean = false + def t4(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t5(t1DecodePattern: T1DecodePattern): Boolean = false + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vssra.vi", + "vssra.vv", + "vssra.vx", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t7(t1DecodePattern: T1DecodePattern): Boolean = false + def t8(t1DecodePattern: T1DecodePattern): Boolean = false + def t9(t1DecodePattern: T1DecodePattern): Boolean = false + def t10(t1DecodePattern: T1DecodePattern): Boolean = false + def t11(t1DecodePattern: T1DecodePattern): Boolean = false + def t12(t1DecodePattern: T1DecodePattern): Boolean = false + def t13(t1DecodePattern: T1DecodePattern): Boolean = false + def t14(t1DecodePattern: T1DecodePattern): Boolean = false + def t15(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class ShiftUop(value: ShiftUopType) extends UopDecodeAttribute[ShiftUopType] { + override val description: String = "" +} diff --git a/t1/src/decoder/attribute/topUop.scala b/t1/src/decoder/attribute/topUop.scala index ef0272548..59ee86390 100644 --- a/t1/src/decoder/attribute/topUop.scala +++ b/t1/src/decoder/attribute/topUop.scala @@ -5,37 +5,93 @@ package org.chipsalliance.t1.rtl.decoder.attribute import org.chipsalliance.t1.rtl.decoder.T1DecodePattern +trait TopUopType extends Uop +object TopT0 extends TopUopType +object TopT1 extends TopUopType +object TopT2 extends TopUopType +object TopT3 extends TopUopType +object TopT4 extends TopUopType +object TopT5 extends TopUopType +object TopT6 extends TopUopType +object TopT7 extends TopUopType +object TopDC extends TopUopType + object TopUop { - trait Type extends Uop { - def apply(t1DecodePattern: T1DecodePattern): Boolean + def apply(t1DecodePattern: T1DecodePattern): TopUopType = { + Seq( + t0 _ -> TopT0, + t1 _ -> TopT1, + t2 _ -> TopT2, + t3 _ -> TopT3, + t4 _ -> TopT4, + t5 _ -> TopT5, + t6 _ -> TopT6, + t7 _ -> TopT7, + dc _ -> TopDC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(t1(t1DecodePattern) + || t2(t1DecodePattern) + || t3(t1DecodePattern) + || t4(t1DecodePattern) + || t5(t1DecodePattern) + || t6(t1DecodePattern) + || t7(t1DecodePattern) + || dc(t1DecodePattern) + ) + ) + allMatched.contains(t1DecodePattern.instruction.name) } - case object UP extends Type { - def apply(t1DecodePattern: T1DecodePattern): Boolean = isSlid(this) && isTopuopup(this) + def t1(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfslide1down.vf", + "vslide1down.vx", + "vzext.vf2", + ) + allMatched.contains(t1DecodePattern.instruction.name) } - case object SLID1 extends Type { - def apply(t1DecodePattern: T1DecodePattern): Boolean = isSlid(this) && isTopuopSlid1(this) + def t2(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vslideup.vi", + "vslideup.vx", + "vzext.vf4", + ) + allMatched.contains(t1DecodePattern.instruction.name) } - case object SIGNEXTEND extends Type { - def apply(t1DecodePattern: T1DecodePattern): Boolean = isExtend(this) && isTopuopsignextend(this) + def t3(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfslide1up.vf", + "vslide1up.vx", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) } - case object MA extends Type { - def apply(t1DecodePattern: T1DecodePattern): Boolean = ~(isSlid(this) && isExtend(this)) + def t4(t1DecodePattern: T1DecodePattern): Boolean = false + def t5(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsext.vf2", + ) + allMatched.contains(t1DecodePattern.instruction.name) } - case object Nil extends Type { - def apply(t1DecodePattern: T1DecodePattern): Boolean = { - require(requirement = false, "unreachable") - false - } + def t6(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsext.vf4", + ) + allMatched.contains(t1DecodePattern.instruction.name) } - def apply(t1DecodePattern: T1DecodePattern): Type = { - val tpe = Seq(UP, SLID1, SIGNEXTEND, MA).filter(tpe => - tpe(t1DecodePattern) + def t7(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vsext.vf8", ) - require(tpe.size <= 1) - tpe.headOption.getOrElse(Nil) + allMatched.contains(t1DecodePattern.instruction.name) } + def dc(t1DecodePattern: T1DecodePattern): Boolean = false } -case class TopUop(value: TopUop.Type) extends UopDecodeAttribute[TopUop.Type] { +case class TopUop(value: TopUopType) extends UopDecodeAttribute[TopUopType] { override val description: String = "uop for mask unit." }