diff --git a/elaborator/src/Main.scala b/elaborator/src/Main.scala
index 131af25e88..f6205977ee 100644
--- a/elaborator/src/Main.scala
+++ b/elaborator/src/Main.scala
@@ -54,7 +54,7 @@ object Main {
 
   @main
   case class SubsystemConfig(ipConfig: IPConfig) {
-    def cdeParameter = (new org.chipsalliance.t1.subsystem.VerdesConfig).orElse(new org.chipsalliance.cde.config.Config((_, _, _) => {
+    def cdeParameter = (new org.chipsalliance.t1.subsystem.T1SubsystemConfig).orElse(new org.chipsalliance.cde.config.Config((_, _, _) => {
       case org.chipsalliance.t1.subsystem.T1ConfigPath                              => ipConfig.ipConfig
     }))
   }
@@ -68,7 +68,7 @@ object Main {
     new org.chipsalliance.t1.ipemu.TestBench(ipConfig.generator)
   )
   @main def subsystem(elaborateConfig: ElaborateConfig, subsystemConfig: SubsystemConfig): Unit = elaborateConfig.elaborate(() =>
-    freechips.rocketchip.diplomacy.LazyModule(new org.chipsalliance.t1.subsystem.VerdesSystem()(subsystemConfig.cdeParameter))(freechips.rocketchip.diplomacy.ValName("T1Subsystem"), chisel3.experimental.UnlocatableSourceInfo).module
+    freechips.rocketchip.diplomacy.LazyModule(new org.chipsalliance.t1.subsystem.T1SubsystemSystem()(subsystemConfig.cdeParameter))(freechips.rocketchip.diplomacy.ValName("T1Subsystem"), chisel3.experimental.UnlocatableSourceInfo).module
   )
   @main def subsystememu(elaborateConfig: ElaborateConfig, subsystemConfig: SubsystemConfig): Unit = elaborateConfig.elaborate(() =>
     new org.chipsalliance.t1.subsystememu.TestHarness()(subsystemConfig.cdeParameter)
diff --git a/fpga/src/MidShell.scala b/fpga/src/MidShell.scala
index 9536006d9e..d4379e266c 100644
--- a/fpga/src/MidShell.scala
+++ b/fpga/src/MidShell.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4BundleParameters}
 import freechips.rocketchip.diplomacy.LazyModule
 import org.chipsalliance.cde.config.Parameters
-import org.chipsalliance.t1.subsystem.VerdesSystem
+import org.chipsalliance.t1.subsystem.T1SubsystemSystem
 
 class MidShell(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle{
@@ -248,7 +248,7 @@ class MidShell(implicit val p: Parameters) extends Module {
     val axiltoaxi = Module(new AXILtoAXI(4))
     axiltoaxi.io.axil <> dutUART.io.mmio
 
-    val ldut = LazyModule(new VerdesSystem)
+    val ldut = LazyModule(new T1SubsystemSystem)
     val dut = Module(ldut.module)
 
     ldut.resetVector := cpuResetVector
diff --git a/subsystem/src/Subsystem.scala b/subsystem/src/Subsystem.scala
index 32706f7dd7..ff32d27b5b 100644
--- a/subsystem/src/Subsystem.scala
+++ b/subsystem/src/Subsystem.scala
@@ -16,7 +16,7 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.t1.rocketcore.{RocketTileAttachParams, RocketTileParams}
 import org.chipsalliance.t1.rockettile.BuildVector
 
-class VerdesConfig
+class T1SubsystemConfig
   extends Config(
     new Config((site, here, up) => {
       case SystemBusKey => SystemBusParams(
@@ -87,12 +87,12 @@ class VerdesConfig
       .orElse(new WithNExtTopInterrupts(1))
       // 1 MHz
       .orElse(new WithTimebase(BigInt(1000000)))
-      .orElse(new WithDTS("sequencer,verdes", Nil))
+      .orElse(new WithDTS("chipsalliance,t1", Nil))
       .orElse(new WithIncoherentBusTopology)
       .orElse(new BaseSubsystemConfig)
   )
 
-class VerdesSystem(implicit p: Parameters) extends BaseSubsystem
+class T1SubsystemSystem(implicit p: Parameters) extends BaseSubsystem
   with InstantiatesHierarchicalElements
   with HasTileNotificationSinks
   with HasTileInputConstants
@@ -108,12 +108,12 @@ class VerdesSystem(implicit p: Parameters) extends BaseSubsystem
   val resetVectorSourceNode = BundleBridgeSource[UInt]()
   tileResetVectorNodes.values.foreach(_ := resetVectorSourceNode)
   val resetVector = InModuleBody(resetVectorSourceNode.makeIO())
-  override lazy val module = new VerdesSystemModuleImp(this)
+  override lazy val module = new T1SubsystemModuleImp(this)
   lazy val debugOpt: Option[TLDebugModule] = None
 }
 
-class VerdesSystemModuleImp[+L <: VerdesSystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
+class T1SubsystemModuleImp[+L <: T1SubsystemSystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
   with HasHierarchicalElementsRootContextModuleImp
   with HasRTCModuleImp
   with HasExtInterruptsModuleImp
-  with DontTouch
\ No newline at end of file
+  with DontTouch
diff --git a/subsystememu/src/Testbench.scala b/subsystememu/src/Testbench.scala
index 93f492ae87..004c77ea8f 100644
--- a/subsystememu/src/Testbench.scala
+++ b/subsystememu/src/Testbench.scala
@@ -8,11 +8,11 @@ import chisel3.probe._
 import freechips.rocketchip.diplomacy.LazyModule
 import freechips.rocketchip.subsystem.ExtMem
 import org.chipsalliance.cde.config.Parameters
-import org.chipsalliance.t1.subsystem.VerdesSystem
+import org.chipsalliance.t1.subsystem.T1SubsystemSystem
 import org.chipsalliance.t1.subsystememu.dpi._
 
 class TestHarness(implicit val p: Parameters) extends RawModule {
-  val ldut = LazyModule(new VerdesSystem)
+  val ldut = LazyModule(new T1SubsystemSystem)
   val dpiClockGen = Module(new ClockGen(ClockGenParameter(2)))
   val clock = read(dpiClockGen.clock)
   val reset = read(dpiClockGen.reset)