From be43dbb9fdc3b0e4a284fc2065ad069696eac817 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Thu, 9 May 2024 06:13:28 +0800 Subject: [PATCH] [rtl] remove unused VectorWrapper --- t1/src/VectorWrapper.scala | 42 -------------------------------------- 1 file changed, 42 deletions(-) delete mode 100644 t1/src/VectorWrapper.scala diff --git a/t1/src/VectorWrapper.scala b/t1/src/VectorWrapper.scala deleted file mode 100644 index ec10d8a357..0000000000 --- a/t1/src/VectorWrapper.scala +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileCopyrightText: 2022 Jiuyang Liu - -package org.chipsalliance.t1.rtl - -import chisel3._ -import tilelink._ -import chisel3.util._ - -class InstructionQueueBundle(parameter: T1Parameter) extends Bundle { - val instruction = new VRequest(parameter.xLen) - val csrInterface = new CSRInterface(parameter.laneParam.vlMaxBits) -} - -class VectorWrapper(parameter: T1Parameter) extends Module { - val request: DecoupledIO[VRequest] = IO(Flipped(Decoupled(new VRequest(parameter.xLen)))) - val response: ValidIO[VResponse] = IO(Valid(new VResponse(parameter.xLen))) - val csrInterface: CSRInterface = IO(Input(new CSRInterface(parameter.laneParam.vlMaxBits))) - val storeBufferClear: Bool = IO(Input(Bool())) - // TODO: multiple LSU support. - val memoryPorts: Vec[TLBundle] = IO(Vec(parameter.lsuBankParameters.size, parameter.tlParam.bundle())) - - // v主体 - val vector: T1 = Module(new T1(parameter)) - // 先忽视v set 类型的指令 - val vSetInstruction: Bool = (request.bits.instruction(6, 0) === "0b1010111".U) && (request.bits.instruction(14, 12) === 7.U) - val instructionQueue: Queue[InstructionQueueBundle] = Module(new Queue(new InstructionQueueBundle(parameter), parameter.instructionQueueSize)) - // queue 入口的连接,csr信息伴随指令走 - instructionQueue.io.enq.valid := request.valid && !vSetInstruction - request.ready := instructionQueue.io.enq.ready || vSetInstruction - instructionQueue.io.enq.bits.instruction := request.bits - instructionQueue.io.enq.bits.csrInterface := csrInterface - - memoryPorts.zip(vector.memoryPorts).foreach {case (sink, source) => sink <> source} - vector.request.valid := instructionQueue.io.deq.valid - vector.request.bits := instructionQueue.io.deq.bits.instruction - instructionQueue.io.deq.ready := vector.request.ready - vector.csrInterface := instructionQueue.io.deq.bits.csrInterface - - response := vector.response - vector.storeBufferClear := storeBufferClear -}