From b75bf7dc553bbea8dce9513a18e99b2ac45f5d68 Mon Sep 17 00:00:00 2001 From: SharzyL Date: Mon, 13 May 2024 23:40:10 +0800 Subject: [PATCH] [nix] generate elaborate config in repo, filter fp inconsistency --- .gitignore | 1 + Makefile | 5 +- configgen/generated/blastoise.json | 252 +++++++++++++++++++ configgen/generated/machamp.json | 236 ++++++++++++++++++ configgen/generated/sandslash.json | 284 ++++++++++++++++++++++ configgen/src/Main.scala | 105 ++------ nix/overlay.nix | 4 +- nix/t1/default.nix | 35 ++- nix/t1/t1.nix | 2 +- script/src/Main.scala | 39 +-- tests/asm/default.nix | 5 +- tests/asm/fpsmoke/isFp | 0 tests/builder.nix | 22 +- tests/codegen/default.nix | 23 +- tests/default.nix | 14 +- tests/intrinsic/default.nix | 5 +- tests/intrinsic/linear_normalization/isFp | 0 tests/intrinsic/softmax/isFp | 0 tests/mlir/default.nix | 5 +- tests/perf/llama/default.nix | 2 + 20 files changed, 863 insertions(+), 176 deletions(-) create mode 100644 configgen/generated/blastoise.json create mode 100644 configgen/generated/machamp.json create mode 100644 configgen/generated/sandslash.json create mode 100644 tests/asm/fpsmoke/isFp create mode 100644 tests/intrinsic/linear_normalization/isFp create mode 100644 tests/intrinsic/softmax/isFp diff --git a/.gitignore b/.gitignore index 4ad7ccafd3..c4d6197ba6 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,4 @@ __pycache__ .direnv .envrc test-results +target diff --git a/Makefile b/Makefile index 3bdaf6c3a2..6664c714c0 100644 --- a/Makefile +++ b/Makefile @@ -50,5 +50,8 @@ list-testcases: .PHONY: list-configs list-configs: - nix run '.#t1.configgen' -- listConfigs | less -R + nix run '.#t1.configgen' -- listConfigs +.PHONY: update-configs +update-configs: + nix run '.#t1.configgen' -- listConfigs diff --git a/configgen/generated/blastoise.json b/configgen/generated/blastoise.json new file mode 100644 index 0000000000..081bcb4241 --- /dev/null +++ b/configgen/generated/blastoise.json @@ -0,0 +1,252 @@ +{ + "parameter": { + "vLen": 512, + "dLen": 256, + "extensions": [ + "Zve32f" + ], + "lsuBankParameters": [ + { + "name": "scalar", + "region": "b00??????????????????????????????", + "beatbyte": 8, + "accessScalar": true + }, + { + "name": "ddrBank0", + "region": "b01???????????????????????00?????\nb10???????????????????????00?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank1", + "region": "b01???????????????????????01?????\nb10???????????????????????01?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank2", + "region": "b01???????????????????????10?????\nb10???????????????????????10?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank3", + "region": "b01???????????????????????11?????\nb10???????????????????????11?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank0", + "region": "b11000000000?????????????000?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank1", + "region": "b11000000000?????????????001?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank2", + "region": "b11000000000?????????????010?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank3", + "region": "b11000000000?????????????011?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank4", + "region": "b11000000000?????????????100?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank5", + "region": "b11000000000?????????????101?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank6", + "region": "b11000000000?????????????110?????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank7", + "region": "b11000000000?????????????111?????", + "beatbyte": 8, + "accessScalar": false + } + ], + "vrfBankSize": 1, + "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rwp1rw", + "vfuInstantiateParameter": { + "slotCount": 4, + "logicModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.MaskedLogic" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "aluModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 0 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 1 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 2 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 3 + ] + ] + ], + "shifterModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneShifter" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "mulModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 2 + }, + "generator": "org.chipsalliance.t1.rtl.LaneMul" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "divModuleParameters": [], + "divfpModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneDivFP" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "otherModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "vlMaxBits": 10, + "groupNumberBits": 4, + "laneNumberBits": 3, + "dataPathByteWidth": 4, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.OtherUnit" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "floatModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 3 + }, + "generator": "org.chipsalliance.t1.rtl.LaneFloat" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ] + } + }, + "generator": "org.chipsalliance.t1.rtl.T1" +} \ No newline at end of file diff --git a/configgen/generated/machamp.json b/configgen/generated/machamp.json new file mode 100644 index 0000000000..39a3fa1ba1 --- /dev/null +++ b/configgen/generated/machamp.json @@ -0,0 +1,236 @@ +{ + "parameter": { + "vLen": 1024, + "dLen": 512, + "extensions": [ + "Zve32x" + ], + "lsuBankParameters": [ + { + "name": "scalar", + "region": "b00??????????????????????????????", + "beatbyte": 8, + "accessScalar": true + }, + { + "name": "ddrBank0", + "region": "b01??????????????????????00??????\nb10??????????????????????00??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank1", + "region": "b01??????????????????????01??????\nb10??????????????????????01??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank2", + "region": "b01??????????????????????10??????\nb10??????????????????????10??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank3", + "region": "b01??????????????????????11??????\nb10??????????????????????11??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank0", + "region": "b11000000000????????????000??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank1", + "region": "b11000000000????????????001??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank2", + "region": "b11000000000????????????010??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank3", + "region": "b11000000000????????????011??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank4", + "region": "b11000000000????????????100??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank5", + "region": "b11000000000????????????101??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank6", + "region": "b11000000000????????????110??????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank7", + "region": "b11000000000????????????111??????", + "beatbyte": 8, + "accessScalar": false + } + ], + "vrfBankSize": 2, + "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rp1w", + "vfuInstantiateParameter": { + "slotCount": 4, + "logicModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.MaskedLogic" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "aluModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 0 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 1 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 2 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 3 + ] + ] + ], + "shifterModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneShifter" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "mulModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 2 + }, + "generator": "org.chipsalliance.t1.rtl.LaneMul" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "divModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneDiv" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "divfpModuleParameters": [], + "otherModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "vlMaxBits": 11, + "groupNumberBits": 4, + "laneNumberBits": 4, + "dataPathByteWidth": 4, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.OtherUnit" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "floatModuleParameters": [] + } + }, + "generator": "org.chipsalliance.t1.rtl.T1" +} \ No newline at end of file diff --git a/configgen/generated/sandslash.json b/configgen/generated/sandslash.json new file mode 100644 index 0000000000..4f1c3ed8a4 --- /dev/null +++ b/configgen/generated/sandslash.json @@ -0,0 +1,284 @@ +{ + "parameter": { + "vLen": 4096, + "dLen": 1024, + "extensions": [ + "Zve32x" + ], + "lsuBankParameters": [ + { + "name": "scalar", + "region": "b00??????????????????????????????", + "beatbyte": 8, + "accessScalar": true + }, + { + "name": "ddrBank0", + "region": "b01?????????????????????00???????\nb10?????????????????????00???????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank1", + "region": "b01?????????????????????01???????\nb10?????????????????????01???????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank2", + "region": "b01?????????????????????10???????\nb10?????????????????????10???????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "ddrBank3", + "region": "b01?????????????????????11???????\nb10?????????????????????11???????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank0", + "region": "b1100000000?????????0000?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank1", + "region": "b1100000000?????????0001?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank2", + "region": "b1100000000?????????0010?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank3", + "region": "b1100000000?????????0011?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank4", + "region": "b1100000000?????????0100?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank5", + "region": "b1100000000?????????0101?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank6", + "region": "b1100000000?????????0110?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank7", + "region": "b1100000000?????????0111?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank8", + "region": "b1100000000?????????1000?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank9", + "region": "b1100000000?????????1001?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank10", + "region": "b1100000000?????????1010?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank11", + "region": "b1100000000?????????1011?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank12", + "region": "b1100000000?????????1100?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank13", + "region": "b1100000000?????????1101?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank14", + "region": "b1100000000?????????1110?????????", + "beatbyte": 8, + "accessScalar": false + }, + { + "name": "sramBank15", + "region": "b1100000000?????????1111?????????", + "beatbyte": 8, + "accessScalar": false + } + ], + "vrfBankSize": 4, + "vrfRamType": "org.chipsalliance.t1.rtl.vrf.RamType.p0rw", + "vfuInstantiateParameter": { + "slotCount": 4, + "logicModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.MaskedLogic" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "aluModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 0 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 1 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 2 + ] + ], + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneAdder" + }, + [ + 3 + ] + ] + ], + "shifterModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneShifter" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "mulModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 2 + }, + "generator": "org.chipsalliance.t1.rtl.LaneMul" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "divModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.LaneDiv" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "divfpModuleParameters": [], + "otherModuleParameters": [ + [ + { + "parameter": { + "datapathWidth": 32, + "vlMaxBits": 13, + "groupNumberBits": 5, + "laneNumberBits": 5, + "dataPathByteWidth": 4, + "latency": 1 + }, + "generator": "org.chipsalliance.t1.rtl.OtherUnit" + }, + [ + 0, + 1, + 2, + 3 + ] + ] + ], + "floatModuleParameters": [] + } + }, + "generator": "org.chipsalliance.t1.rtl.T1" +} \ No newline at end of file diff --git a/configgen/src/Main.scala b/configgen/src/Main.scala index bb623d71a5..b1ae9527a3 100644 --- a/configgen/src/Main.scala +++ b/configgen/src/Main.scala @@ -18,8 +18,8 @@ object Main { def read(strs: Seq[String]): Either[String, os.Path] = Right(os.Path(strs.head, os.pwd)) } implicit class EmitVParameter(p: T1Parameter) { - def emit(targetDir: os.Path) = os.write( - targetDir / "config.json", + def emit(targetFile: os.Path) = os.write( + targetFile, upickle.default.write(SerializableModuleGenerator(classOf[T1], p), indent = 2) ) } @@ -44,9 +44,26 @@ object Main { ) } + @main def updateConfigs( + @arg(name = "project-dir", short = 't') projectDir: os.Path = os.pwd + ): Unit = { + val declaredMethods = + Main.getClass().getDeclaredMethods().filter(m => m.getParameterTypes().mkString(", ") == "class os.Path, boolean") + + import scala.io.AnsiColor._ + + val generatedDir = projectDir / "configgen" / "generated" + os.list(generatedDir).foreach(f => os.remove(f)) + + declaredMethods.foreach(configgen => { + val configName = configgen.getName() + configgen.invoke(Main, generatedDir / s"$configName.json", true) + }) + } + // DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8 @main def blastoise( - @arg(name = "target-dir", short = 't') targetDir: os.Path, + @arg(name = "target-file", short = 't') targetFile: os.Path, @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true ): T1Parameter = { val vLen = 512 @@ -111,13 +128,13 @@ object Main { Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))) ) ) - if (doEmit) param.emit(targetDir) + if (doEmit) param.emit(targetFile) param } // DLEN512 VLEN1K ; NOFP; VRF p0r,p1w bank2; LSU bank8 beatbyte 16 @main def machamp( - @arg(name = "target-dir", short = 't') targetDir: os.Path, + @arg(name = "target-file", short = 't') targetFile: os.Path, @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true ): T1Parameter = { val vLen = 1024 @@ -188,13 +205,13 @@ object Main { floatModuleParameters = Seq() ) ) - if (doEmit) param.emit(targetDir) + if (doEmit) param.emit(targetFile) param } // DLEN1K VLEN4K ; NOFP; VRF p0rw bank4; LSU bank16 beatbyte 16 @main def sandslash( - @arg(name = "target-dir", short = 't') targetDir: os.Path, + @arg(name = "target-file", short = 't') targetFile: os.Path, @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true ): T1Parameter = { val vLen = 4096 @@ -267,79 +284,7 @@ object Main { floatModuleParameters = Seq() ) ) - if (doEmit) param.emit(targetDir) - param - } - - // DLEN2K VLEN16K; NOFP; VRF p0rw bank8; LSU bank8 beatbyte 64 - @main def alakazam( - @arg(name = "target-dir", short = 't') targetDir: os.Path, - @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true - ): T1Parameter = { - val vLen = 16384 - val dLen = 2048 - val param = T1Parameter( - vLen, - dLen, - extensions = Seq("Zve32x"), - // banks=8 dLen=2048 - lsuBankParameters = - // scalar bank 0-1G - Seq( - BitSet(BitPat("b00??????????????????????????????")) - ).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++ - // ddr bank 1G-3G 512M/bank - Seq( - BitSet(BitPat("b01????????????????????00????????"), BitPat("b10????????????????????00????????")), - BitSet(BitPat("b01????????????????????01????????"), BitPat("b10????????????????????01????????")), - BitSet(BitPat("b01????????????????????10????????"), BitPat("b10????????????????????10????????")), - BitSet(BitPat("b01????????????????????11????????"), BitPat("b10????????????????????11????????")) - ).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 4, false) } ++ - // sRam bank 3G+ 256K/bank, 8banks - Seq( - BitSet(BitPat("b11000000000??????????000????????")), - BitSet(BitPat("b11000000000??????????001????????")), - BitSet(BitPat("b11000000000??????????010????????")), - BitSet(BitPat("b11000000000??????????011????????")), - BitSet(BitPat("b11000000000??????????100????????")), - BitSet(BitPat("b11000000000??????????101????????")), - BitSet(BitPat("b11000000000??????????110????????")), - BitSet(BitPat("b11000000000??????????111????????")) - ).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 4, false) }, - vrfBankSize = 8, - vrfRamType = RamType.p0rw, - vfuInstantiateParameter = VFUInstantiateParameter( - slotCount = 4, - logicModuleParameters = Seq( - (SerializableModuleGenerator(classOf[MaskedLogic], LogicParam(32, 0)), Seq(0, 1, 2, 3)) - ), - aluModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 0)), Seq(0)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 0)), Seq(1)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 0)), Seq(2)), - (SerializableModuleGenerator(classOf[LaneAdder], LaneAdderParam(32, 0)), Seq(3)) - ), - shifterModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneShifter], LaneShifterParameter(32, 0)), Seq(0, 1, 2, 3)) - ), - mulModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneMul], LaneMulParam(32, 2)), Seq(0, 1, 2, 3)) - ), - divModuleParameters = Seq( - (SerializableModuleGenerator(classOf[LaneDiv], LaneDivParam(32, 0)), Seq(0, 1, 2, 3)) - ), - divfpModuleParameters = Seq(), - otherModuleParameters = - Seq(( - SerializableModuleGenerator( - classOf[OtherUnit], - OtherUnitParam(32, log2Ceil(vLen) + 1, log2Ceil(vLen * 8 / dLen), log2Ceil(dLen / 32), 4, 0) - ), - Seq(0, 1, 2, 3))), - floatModuleParameters = Seq() - ) - ) - if (doEmit) param.emit(targetDir) + if (doEmit) param.emit(targetFile) param } diff --git a/nix/overlay.nix b/nix/overlay.nix index f542aa9231..bf583a7721 100644 --- a/nix/overlay.nix +++ b/nix/overlay.nix @@ -84,7 +84,5 @@ in }; }; - t1 = final.callPackage ./t1 { - allConfigs = (builtins.fromJSON (builtins.readFile ../configgen/all-configs.json)).configs; - }; + t1 = final.callPackage ./t1 { }; } diff --git a/nix/t1/default.nix b/nix/t1/default.nix index 0f8254b060..0421227be0 100644 --- a/nix/t1/default.nix +++ b/nix/t1/default.nix @@ -4,17 +4,23 @@ , useMoldLinker , newScope -, rv32-stdenv -, runCommand , pkgsX86 - -, allConfigs }: let moldStdenv = useMoldLinker stdenv; -in + configsDirectory = ../../configgen/generated; + + # allConfigs is a (configName -> configJsonPath) map + allConfigs = lib.mapAttrs' + (fileName: fileType: + assert fileType == "regular" && lib.hasSuffix ".json" fileName; + lib.nameValuePair + (lib.removeSuffix ".json" fileName) + (lib.path.append configsDirectory fileName)) + (builtins.readDir configsDirectory); +in lib.makeScope newScope (self: let @@ -32,7 +38,7 @@ lib.makeScope newScope riscv-opcodes-src = self.submodules.sources.riscv-opcodes.src; } // - lib.genAttrs allConfigs (configName: + lib.mapAttrs (configName: configPath: # by using makeScope, callPackage can send the following attributes to package parameters lib.makeScope self.newScope (innerSelf: rec { recurseForDerivations = true; @@ -40,19 +46,8 @@ lib.makeScope newScope # For package name concatenate inherit configName; - elaborateConfigJson = runCommand "${configName}-config.json" { } '' - ${self.configgen}/bin/configgen ${configName} -t . - mv config.json $out - ''; - - _caseBuilders = lib.makeScope innerSelf.newScope (buildersSelf: { - mkMlirCase = buildersSelf.callPackage ./testcases/make-mlir-case.nix { stdenv = rv32-stdenv; }; - mkIntrinsicCase = buildersSelf.callPackage ./testcases/make-intrinsic-case.nix { stdenv = rv32-stdenv; }; - mkAsmCase = buildersSelf.callPackage ./testcases/make-asm-case.nix { stdenv = rv32-stdenv; }; - mkCodegenCase = buildersSelf.callPackage ./testcases/make-codegen-case.nix { stdenv = rv32-stdenv; }; - mkBenchCase = buildersSelf.callPackage ../../tests/rvv_bench/make-bench-case.nix { stdenv = rv32-stdenv; }; - - }); + elaborateConfigJson = configPath; + elaborateConfig = builtins.fromJSON (lib.readFile configPath); cases = innerSelf.callPackage ../../tests { }; @@ -88,5 +83,5 @@ lib.makeScope newScope release = innerSelf.callPackage ./release { }; }) - ) + ) allConfigs ) diff --git a/nix/t1/t1.nix b/nix/t1/t1.nix index 67df566bb3..42898aaabe 100644 --- a/nix/t1/t1.nix +++ b/nix/t1/t1.nix @@ -29,7 +29,7 @@ let ./../../emuhelper ./../../ipemu/src ./../../elaborator - ./../../configgen + ./../../configgen/src ]; }; diff --git a/script/src/Main.scala b/script/src/Main.scala index d31ab9b1a0..f485679b10 100644 --- a/script/src/Main.scala +++ b/script/src/Main.scala @@ -82,29 +82,9 @@ object Main: end resolveEmulatorPath def resolveElaborateConfig( - outputDir: os.Path, configName: String ): os.Path = - if (os.exists(outputDir / "config.json")) then - os.remove.all(outputDir / "config.json") - - val cfgPath = os.Path(configName, os.pwd) - if (os.exists(cfgPath)) then return cfgPath - - val nixArgs = Seq( - "nix", - "run", - "--no-warn-dirty", - ".#t1.configgen", - "--", - configName, - "-t", - outputDir.toString - ) - Logger.trace(s"Runnning `${nixArgs.mkString(" ")}` to get config") - os.proc(nixArgs).call() - - outputDir / "config.json" + os.pwd / "configgen" / "generated" / s"$configName.json" end resolveElaborateConfig def prepareOutputDir( @@ -233,7 +213,7 @@ object Main: else resolveEmulatorPath(config, "ip", trace.value) import scala.util.chaining._ - val elaborateConfig = resolveElaborateConfig(outputPath, config) + val elaborateConfig = resolveElaborateConfig(config) .pipe(os.read) .pipe(text => ujson.read(text)) val tck = scala.math.pow(10, 3) / dramsim3Frequency @@ -660,24 +640,9 @@ object Main: import scala.util.chaining._ val testPlans: Seq[String] = emulatorConfigs.flatMap: configName => val allCasesPath = nixBuild(s".#t1.$configName.cases.all") - // We can't filter it in nix as it will make the whole t1 attribute become IFD(Import From Derivation) attribute. - val isFp = nixBuild(s".#t1.$configName.elaborateConfigJson") - // We get the elaborate config JSON file [p]ath, read it as [r]aw string - .pipe(p => os.read(os.Path(p))) - // We get the [r]aw JSON string, parse it to ujson object - .pipe(r => ujson.read(r)) - // We get the u[j]son object, get the first item of the .parameter.extensions field - .pipe(j => j.obj("parameter").obj("extensions").arr.head.str) - // Now we have the extension, test if it is Zve32f - .pipe(ext => ext == "Zve32f") - // Now we know that the emulator support FP or not, generate test plan base on this information os.walk(os.Path(allCasesPath) / "configs") .filter: path => path.ext == "json" - .filter: path => - os.read(path) - .pipe(raw => ujson.read(raw)) - .pipe(json => json.obj("fp").bool == isFp) .map: path => // configs/ directory have a list of .json files, we need those val testName = path.segments.toSeq.last.stripSuffix(".json") diff --git a/tests/asm/default.nix b/tests/asm/default.nix index bb61c0aebe..4bd751df85 100644 --- a/tests/asm/default.nix +++ b/tests/asm/default.nix @@ -1,4 +1,5 @@ -{ linkerScript +{ lib +, linkerScript , makeBuilder , findAndBuild , t1main @@ -12,6 +13,8 @@ let src = sourcePath; + isFp = lib.pathExists (lib.path.append sourcePath "isFp"); + buildPhase = '' runHook preBuild diff --git a/tests/asm/fpsmoke/isFp b/tests/asm/fpsmoke/isFp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/builder.nix b/tests/builder.nix index b9b62f0320..2a0d0cf5a1 100644 --- a/tests/builder.nix +++ b/tests/builder.nix @@ -1,7 +1,7 @@ # args from scope `casesSelf` { stdenv , jq -, elaborateConfigJson +, elaborateConfig }: # args from makeBuilder @@ -36,21 +36,6 @@ stdenv.mkDerivation (self: rec { "-O3" ]; - configurePhase = '' - export vLen=$(${jqBin} --exit-status --raw-output ".parameter.vLen" ${elaborateConfigJson}) - - is32BitLen=$(${jqBin} -r '.parameter.extensions[] | test("ve32")' ${elaborateConfigJson}) - if [[ "$is32BitLen" = "true" ]] ; then - export xLen=32 - else - export xLen=64 - fi - - isFp=$(${jqBin} -r '.parameter.extensions[] | test("f")' ${elaborateConfigJson}) - - echo "Set vLen=$vLen xLen=$xLen isFp=$isFp" - ''; - installPhase = '' runHook preInstall @@ -60,11 +45,8 @@ stdenv.mkDerivation (self: rec { ${jqBin} --null-input \ --arg name ${pname} \ --arg type ${casePrefix} \ - --argjson xLen "$xLen" \ - --argjson vLen "$vLen" \ - --argjson fp "$isFp" \ --arg elfPath "$out/bin/${pname}.elf" \ - '{ "name": $name, "type": $type, "xLen": $xLen, "vLen": $vLen, "fp": $fp, "elf": { "path": $elfPath } }' \ + '{ "name": $name, "elf": { "path": $elfPath } }' \ > $out/${pname}.json runHook postInstall diff --git a/tests/codegen/default.nix b/tests/codegen/default.nix index b0bb1c1df3..e771efddb4 100644 --- a/tests/codegen/default.nix +++ b/tests/codegen/default.nix @@ -2,13 +2,16 @@ , linkerScript , rvv-codegen , makeBuilder +, xLen +, vLen +, isFp }: let builder = makeBuilder { casePrefix = "codegen"; }; makeCaseName = lib.replaceStrings [ "." ] [ "_" ]; - build = { rawCaseName, fp }: + build = { rawCaseName, isFp }: builder rec { caseName = makeCaseName rawCaseName; @@ -19,12 +22,14 @@ let dontUnpack = true; + inherit isFp; + buildPhase = '' runHook preBuild ${rvv-codegen}/bin/single \ - -VLEN "$vLen" \ - -XLEN "$xLen" \ + -VLEN "${toString vLen}" \ + -XLEN "${toString xLen}" \ -repeat 16 \ -testfloat3level 2 \ -configfile ${rvv-codegen}/configs/${rawCaseName}.toml \ @@ -45,7 +50,7 @@ let meta.description = "test case '${caseName}' generated by codegen"; }; - buildTestsFromFile = file: { fp ? false }: + buildTestsFromFile = file: { isFp ? false }: with lib; let rawCaseNames = lib.splitString "\n" (lib.fileContents file); @@ -54,13 +59,17 @@ let (map (rawCaseName: nameValuePair (makeCaseName rawCaseName) - (build { inherit rawCaseName fp; }) + (build { inherit rawCaseName isFp; }) ) rawCaseNames)); commonTests = buildTestsFromFile ./common.txt { }; - fpTests = buildTestsFromFile ./fp.txt { fp = true; }; + fpTests = buildTestsFromFile ./fp.txt { isFp = true; }; in -lib.recurseIntoAttrs (commonTests // fpTests) +lib.recurseIntoAttrs ( + if isFp + then commonTests // fpTests + else commonTests +) diff --git a/tests/default.nix b/tests/default.nix index b819d386db..1afd4faa38 100644 --- a/tests/default.nix +++ b/tests/default.nix @@ -1,10 +1,16 @@ { lib +, elaborateConfig , newScope , rv32-stdenv , runCommand }: let + extension = lib.head elaborateConfig.parameter.extensions; + xLen = if lib.hasInfix "ve32" extension then 32 else 64; + isFp = lib.hasInfix "f" extension; + vLen = elaborateConfig.parameter.vLen; + scope = lib.recurseIntoAttrs (lib.makeScope newScope (casesSelf: { makeBuilder = casesSelf.callPackage ./builder.nix { }; @@ -14,7 +20,7 @@ let (lib.filterAttrs (name: type: type == "directory" && ! lib.hasPrefix "_" name)) # prepend path with base directory (lib.mapAttrs (subDirName: _: (lib.path.append dir subDirName))) - # build + # build. If {sourcePath}/default.nix exists, call it. Otherwise call the generic builder (lib.mapAttrs (caseName: sourcePath: if builtins.pathExists "${sourcePath}/default.nix" then casesSelf.callPackage sourcePath { } @@ -23,14 +29,14 @@ let inherit caseName sourcePath; }) ) + (lib.filterAttrs (caseName: caseDrv: assert caseDrv ? isFp; caseDrv.isFp -> isFp)) ]); t1main = ./t1_main.S; linkerScript = ./t1.ld; stdenv = rv32-stdenv; - xLen = 32; - vLen = 1024; - fp = false; + + inherit xLen vLen isFp; mlir = casesSelf.callPackage ./mlir { }; intrinsic = casesSelf.callPackage ./intrinsic { }; diff --git a/tests/intrinsic/default.nix b/tests/intrinsic/default.nix index c878c45f4c..07a108da62 100644 --- a/tests/intrinsic/default.nix +++ b/tests/intrinsic/default.nix @@ -1,4 +1,5 @@ -{ linkerScript +{ lib +, linkerScript , makeBuilder , findAndBuild , t1main @@ -12,6 +13,8 @@ let src = sourcePath; + isFp = lib.pathExists (lib.path.append sourcePath "isFp"); + buildPhase = '' runHook preBuild diff --git a/tests/intrinsic/linear_normalization/isFp b/tests/intrinsic/linear_normalization/isFp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/intrinsic/softmax/isFp b/tests/intrinsic/softmax/isFp new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/mlir/default.nix b/tests/mlir/default.nix index 134301e2d1..6ebb29fe2d 100644 --- a/tests/mlir/default.nix +++ b/tests/mlir/default.nix @@ -1,4 +1,5 @@ -{ linkerScript +{ lib +, linkerScript , buddy-mlir , makeBuilder , findAndBuild @@ -13,6 +14,8 @@ let src = sourcePath; + isFp = lib.pathExists (lib.path.append sourcePath "isFp"); + nativeBuildInputs = [ buddy-mlir ]; buddyOptArgs = [ diff --git a/tests/perf/llama/default.nix b/tests/perf/llama/default.nix index 7d1e1599c4..40ec2f761d 100644 --- a/tests/perf/llama/default.nix +++ b/tests/perf/llama/default.nix @@ -21,6 +21,8 @@ let in build { + isFp = true; + caseName = "llama"; buildInputs = [ emurt ];