From b50ecf91baf4d6ad9c6b5e755efe14cf4a12493d Mon Sep 17 00:00:00 2001
From: Avimitin <dev@avimit.in>
Date: Fri, 30 Aug 2024 14:21:34 +0800
Subject: [PATCH] [tests] remove -riscv-v-vector-bits-min argument

According to LLVM source code, llc will automatically use zvl length
when this argument not specify.

https://llvm.org/doxygen/RISCVSubtarget_8cpp_source.html
Signed-off-by: Avimitin <dev@avimit.in>
---
 tests/pytorch/default.nix | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/pytorch/default.nix b/tests/pytorch/default.nix
index f94d0fa20..95728a114 100644
--- a/tests/pytorch/default.nix
+++ b/tests/pytorch/default.nix
@@ -53,7 +53,6 @@ let
                   -mtriple=riscv32 \
                   -target-abi=ilp32f \
                   -mattr=+m,+f,+zve32f \
-                  -riscv-v-vector-bits-min=128 \
                   --filetype=obj \
                   -o "$llvmir.o"