From b0111831bb801a2117a363c0dc70b7901ac669b9 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Wed, 25 Dec 2024 14:06:39 +0800
Subject: [PATCH] [rtl] fix read in mask unit.

---
 t1/src/Bundles.scala                |  5 +++++
 t1/src/mask/BitLevelMaskWrite.scala |  4 ++--
 t1/src/mask/MaskUnit.scala          | 26 +++++++++++++++-----------
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
index d59a97d75..9b8985ec4 100644
--- a/t1/src/Bundles.scala
+++ b/t1/src/Bundles.scala
@@ -794,3 +794,8 @@ class MaskUnitReadVs1(parameter: T1Parameter) extends Bundle {
 class LaneTokenBundle extends Bundle {
   val maskRequestRelease: Bool = Input(Bool())
 }
+
+class MaskUnitReadPipe(parameter: T1Parameter) extends Bundle {
+  val readSource: UInt = UInt(parameter.laneNumber.W)
+  val dataOffset: UInt = UInt(log2Ceil(parameter.datapathWidth / 8).W)
+}
diff --git a/t1/src/mask/BitLevelMaskWrite.scala b/t1/src/mask/BitLevelMaskWrite.scala
index 5bc73491e..5e30675d1 100644
--- a/t1/src/mask/BitLevelMaskWrite.scala
+++ b/t1/src/mask/BitLevelMaskWrite.scala
@@ -18,7 +18,7 @@ class BitLevelWriteRequest(parameter: T1Parameter) extends Bundle {
 
 class BitLevelMaskWrite(parameter: T1Parameter) extends Module {
   // todo
-  val readVRFLatency: Int = 2
+  val readVRFLatency: Int = 4
 
   val needWAR: Bool = IO(Input(Bool()))
   val vd:      UInt = IO(Input(UInt(5.W)))
@@ -68,7 +68,7 @@ class BitLevelMaskWrite(parameter: T1Parameter) extends Module {
     readPort.bits.vs     := vd + (reqQueue.deq.bits.groupCounter >> readPort.bits.offset.getWidth).asUInt
     readPort.bits.offset := changeUIntSize(reqQueue.deq.bits.groupCounter, readPort.bits.offset.getWidth)
 
-    val readValidPipe   = Pipe(readPort.fire, false.B, readVRFLatency).valid && readResult(index).valid
+    val readValidPipe   = readResult(index).valid
     val readResultValid = !needWAR || readValidPipe
 
     val WARData = (WaitReadQueue.deq.bits.data & WaitReadQueue.deq.bits.bitMask) |
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
index 641ea9bd4..cacc18c08 100644
--- a/t1/src/mask/MaskUnit.scala
+++ b/t1/src/mask/MaskUnit.scala
@@ -130,7 +130,7 @@ class MaskUnit(val parameter: T1Parameter)
 
   // todo: param
   val readQueueSize:          Int = 4
-  val readVRFLatency:         Int = 2
+  val readVRFLatency:         Int = 3
   val maskUnitWriteQueueSize: Int = 8
 
   /** duplicate v0 for mask */
@@ -758,13 +758,15 @@ class MaskUnit(val parameter: T1Parameter)
   val pipeDataOffset: Vec[UInt] = Wire(Vec(parameter.laneNumber, UInt(log2Ceil(parameter.datapathWidth / 8).W)))
 
   readCrossBar.output.zipWithIndex.foreach { case (request, index) =>
+    val readMessageQueue: QueueIO[MaskUnitReadPipe] =
+      Queue.io(new MaskUnitReadPipe(parameter), readVRFLatency + 4)
     val sourceLane = UIntToOH(request.bits.writeIndex)
-    readChannel(index).valid                 := request.valid
+    readChannel(index).valid                 := request.valid && readMessageQueue.enq.ready
     readChannel(index).bits.readSource       := 2.U
     readChannel(index).bits.vs               := request.bits.vs
     readChannel(index).bits.offset           := request.bits.offset
     readChannel(index).bits.instructionIndex := instReg.instructionIndex
-    request.ready                            := readChannel(index).ready
+    request.ready                            := readChannel(index).ready && readMessageQueue.enq.ready
 
     maskedWrite.readChannel(index).ready := readChannel(index).ready
     maskedWrite.readResult(index)        := readResult(index)
@@ -774,15 +776,17 @@ class MaskUnit(val parameter: T1Parameter)
       readChannel(index).bits.offset := maskedWrite.readChannel(index).bits.offset
     }
 
-    // pipe read fire
-    val pipeRead   = Pipe(
-      readChannel(index).fire && !maskDestinationType,
-      sourceLane,
-      readVRFLatency
+    readMessageQueue.enq.valid           := readChannel(index).fire && !maskDestinationType
+    readMessageQueue.enq.bits.readSource := sourceLane
+    readMessageQueue.enq.bits.dataOffset := request.bits.dataOffset
+    readMessageQueue.deq.ready           := readResult(index).valid
+
+    write1HPipe(index)    := Mux(
+      readMessageQueue.deq.valid && readResult(index).valid,
+      readMessageQueue.deq.bits.readSource,
+      0.U(parameter.laneNumber.W)
     )
-    val pipeOffset = Pipe(readChannel(index).fire, request.bits.dataOffset, readVRFLatency)
-    write1HPipe(index)    := Mux(pipeRead.valid, pipeRead.bits, 0.U(parameter.laneNumber.W))
-    pipeDataOffset(index) := pipeOffset.bits
+    pipeDataOffset(index) := readMessageQueue.deq.bits.dataOffset
   }
 
   // Processing read results