From ab9b77549aee6da729d484a01bd113c275af88de Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Thu, 22 Aug 2024 14:55:05 +0800 Subject: [PATCH] [t1rocket] refactor reg/freg write rob. wip --- rocketv/src/FPU.scala | 7 +++++ rocketv/src/RocketCore.scala | 37 +++++++++--------------- t1rocketemu/src/TestBench.scala | 50 ++++++++++++--------------------- 3 files changed, 38 insertions(+), 56 deletions(-) diff --git a/rocketv/src/FPU.scala b/rocketv/src/FPU.scala index b936e85ae1..10d921ef55 100644 --- a/rocketv/src/FPU.scala +++ b/rocketv/src/FPU.scala @@ -15,6 +15,9 @@ class FPUProbe(param: FPUParameter) extends Bundle { val rfWen: Bool = Bool() val rfWaddr: UInt = UInt(5.W) val rfWdata: UInt = UInt((param.fLen + 1).W) + + val waitEn: Bool = Bool() + val waitAddr: UInt = UInt(5.W) } object FPUParameter { @@ -427,6 +430,10 @@ class FPU(val parameter: FPUParameter) probeWire.rfWaddr := Mux(load_wb, load_wb_tag, waddr) probeWire.rfWdata := Mux(load_wb, recode(load_wb_data, load_wb_typeTag), wdata) + // TODO: add this + // probeWire.waitEn := + // probeWire.waitAddr := + } // leaving gated-clock domain val fpuImpl = withClockAndReset(gated_clock, io.reset) { new FPUImpl } } diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index 1a22d2ba1d..7af2ad7130 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -14,25 +14,14 @@ import chisel3.util.{BitPat, Cat, DecoupledIO, Fill, MuxLookup, PriorityEncoder, import org.chipsalliance.rocketv.rvdecoderdbcompat.Causes import org.chipsalliance.rvdecoderdb.Instruction -class RocketRF(param: RocketParameter) extends Bundle { +class RocketProbe(param: RocketParameter) extends Bundle { val rfWen: Bool = Bool() val rfWaddr: UInt = UInt(param.lgNXRegs.W) val rfWdata: UInt = UInt(param.xLen.W) -} - -class RocketROB(param: RocketParameter) extends Bundle { - val commit: Bool = Bool() - val trace: RocketRF = new RocketRF(param) - val shouldWb: Bool = Bool() - val tag: UInt = UInt(5.W) - val wbSetScoreboard: Bool = Bool() - val longLatencyWrite: Bool = Bool() - val isVector: Bool = Bool() -} - -class RocketProbe(param: RocketParameter) extends Bundle { - val rob: RocketROB = new RocketROB(param) // rocket is idle + val waitWen: Bool = new Bool() + val waitWaddr: UInt = UInt(param.lgNXRegs.W) + val isVector: Bool = Bool() val idle: Bool = Bool() } @@ -1088,16 +1077,16 @@ class Rocket(val parameter: RocketParameter) ) when(rfWen) { rf.write(rfWaddr, rfWdata) } - probeWire.rob.trace.rfWen := rfWen - probeWire.rob.trace.rfWaddr := rfWaddr - probeWire.rob.trace.rfWdata := rfWdata + probeWire.rfWen := rfWen + probeWire.rfWaddr := rfWaddr + probeWire.rfWdata := rfWdata + + // TODO: add wait enable + // probeWire.waitEn := + // probeWire.waitAddr := + // FIXME: vectorCSR - probeWire.rob.commit := wbValid - probeWire.rob.shouldWb := wbWxd && wbWaddr =/= 0.U && !wbException - probeWire.rob.tag := wbWaddr - probeWire.rob.wbSetScoreboard := wbSetSboard && wbWen - probeWire.rob.longLatencyWrite := longLatencyWenable - probeWire.rob.isVector := io.t1.map { t1 => + probeWire.isVector := io.t1.map { t1 => wbRegDecodeOutput(parameter.decoderParameter.vector) && !wbRegDecodeOutput(parameter.decoderParameter.vectorCSR) }.getOrElse(false.B) diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index 112b2d058a..3b110e50ab 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -176,48 +176,34 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil val otherUnitProbe = t1Probe.lsuProbe.otherUnitProbe.suggestName("otherUnitProbe") // output the probes - // rocket reg write rob - val robQueue = Module(new Queue(new RocketROB(generator.parameter.rocketParameter), 32)) - val robWriteDataValid = RegInit(0.U(32.W)) - val robWriteData: Seq[UInt] = Seq.tabulate(32){ _ => RegInit(0.U(generator.parameter.xLen.W))} - // push queue - robQueue.io.enq.valid := rocketProbe.rob.commit && rocketProbe.rob.shouldWb - robQueue.io.enq.bits := rocketProbe.rob - - // update rob write - val doEnqSelect: UInt = Mux(rocketProbe.rob.longLatencyWrite, UIntToOH(rocketProbe.rob.trace.rfWaddr), 0.U(32.W)) - val doDeqSelect = Wire(UInt(32.W)) - robWriteDataValid := (doEnqSelect | robWriteDataValid) & (~doDeqSelect).asUInt - robWriteData.zip(doEnqSelect.asBools).foreach {case (d, s) => - d := Mux(s, rocketProbe.rob.trace.rfWdata, d) - } - - // pop queue and output trace - val deqLongLatency: Bool = robQueue.io.deq.bits.wbSetScoreboard - robQueue.io.deq.ready := - // Normal writing - !deqLongLatency || - // Long latency data is ready - (robWriteDataValid & UIntToOH(robQueue.io.deq.bits.tag)).orR - val writeData: UInt = Mux( - deqLongLatency, - Mux1H(UIntToOH(robQueue.io.deq.bits.tag), robWriteData), - robQueue.io.deq.bits.trace.rfWdata - ) - doDeqSelect := Mux(robQueue.io.deq.fire && deqLongLatency, UIntToOH(robQueue.io.deq.bits.tag), 0.U(32.W)) - when(robQueue.io.deq.fire & !robQueue.io.deq.bits.isVector)( + // rocket reg write + when(rocketProbe.rfWen && !rocketProbe.isVector)( printf( - cf"""{"event":"RegWrite","idx":${robQueue.io.deq.bits.tag},"data":"${writeData}%x","cycle":${simulationTime}}\n""" + cf"""{"event":"RegWrite","idx":${rocketProbe.rfWaddr},"data":"${rocketProbe.rfWdata}%x","cycle":${simulationTime}}\n""" ) ) + // TODO: refactor this wait logic + // when(rocketProbe.waitWen && !rocketProbe.isVector)( // should this judge vector? + // printf( + // cf"""{"event":"RegWriteWait","idx":${rocketProbe.waitWaddr},"cycle":${simulationTime}}\n""" + // ) + // ) + // [[option]] rocket fpu reg write t1RocketProbe.fpuProbe.foreach { fpu => when(fpu.rfWen)( printf( - cf"""{"event":"RegWrite","idx":${fpu.rfWaddr},"data":"${fpu.rfWdata}%x","cycle":${simulationTime}}\n""" + cf"""{"event":"FregWrite","idx":${fpu.rfWaddr},"data":"${fpu.rfWdata}%x","cycle":${simulationTime}}\n""" ) ) + + // TODO: refactor this wait logic + // when(fpu.waitWen && !fpu.isVector)( // should this judge vector? + // printf( + // cf"""{"event":"FregWriteWait","idx":${fpu.waitWaddr},"cycle":${simulationTime}}\n""" + // ) + // ) } // t1 vrf write