diff --git a/t1/src/decoder/Decoder.scala b/t1/src/decoder/Decoder.scala index 3233105e8..a3d64491f 100644 --- a/t1/src/decoder/Decoder.scala +++ b/t1/src/decoder/Decoder.scala @@ -187,34 +187,35 @@ object Decoder { Op(tpe, funct6, tpeOp2, funct3, insn.name, special, notLSU=true, vd, opcode) } // case of LSU instructions: `opcodeLoadF` and `opcodeStoreF` - ++ Seq("1", "0").map(fun6End => + ++ instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opcodeLoadF).map{ insn => + val funct6 = insn.encoding.toString.substring(32-31-1, 32-26) Op( "I", // tpe - "?????" + fun6End, + funct6, "?", // tpeOp2 "???", // funct3 - "lsu", + insn.name, None, notLSU = false, "?????", // vd opcodeLoadF ) - ) - ++ Seq("1", "0").map(fun6End => + } + ++ instructions.filter(_.encoding.toString.substring(32-6-1, 32-0) == opcodeStoreF).map{ insn => + val funct6 = insn.encoding.toString.substring(32-31-1, 32-26) Op( "I", // tpe - "?????" + fun6End, + funct6, "?", // tpeOp2 "???", // funct3 - "lsu", + insn.name, None, notLSU = false, "?????", // vd opcodeStoreF ) - ) + } ).toArray - expandedOps.filter(_.tpe != "F" || fpuEnable) } diff --git a/t1/src/decoder/T1DecodePattern.scala b/t1/src/decoder/T1DecodePattern.scala index 5552d0fe6..3dea78d0e 100644 --- a/t1/src/decoder/T1DecodePattern.scala +++ b/t1/src/decoder/T1DecodePattern.scala @@ -11,7 +11,7 @@ import chisel3.util.BitPat import chisel3.util.experimental.decode.DecodePattern import org.chipsalliance.rvdecoderdb.Instruction import org.chipsalliance.t1.rtl.T1Parameter -import org.chipsalliance.t1.rtl.decoder.attribute.isVector +import org.chipsalliance.t1.rtl.decoder.attribute._ @instantiable class T1DecodeAttributeOM extends Class { @@ -57,6 +57,60 @@ case class T1DecodePattern(instruction: Instruction, t1Parameter: T1Parameter) e // use the attribute w/ [[isVector.value]] def isVector: isVector = attribute.isVector(this) + def isAdder: isAdder = attribute.isAdder(this) + def isAverage: isAverage = attribute.isAverage(this) + def isCompress: isCompress = attribute.isCompress(this) + def isCrossread: isCrossread = attribute.isCrossread(this) + def isCrosswrite: isCrosswrite = attribute.isCrosswrite(this) + def isDivider: isDivider = attribute.isDivider(this) + def isDontneedexecuteinlane: isDontneedexecuteinlane = attribute.isDontneedexecuteinlane(this) + def isExtend: isExtend = attribute.isExtend(this) + def isFcompare: isFcompare = attribute.isFcompare(this) + def isFfo: isFfo = attribute.isFfo(this) + def isFirstwiden: isFirstwiden = attribute.isFirstwiden(this) + def isFloatmul: isFloatmul = attribute.isFloatmul(this) + def isFloat: isFloat = attribute.isFloat(this) + def isFloattype: isFloattype = attribute.isFloattype(this) + def isFma: isFma = attribute.isFma(this) + def isFother: isFother = attribute.isFother(this) + def isGather16: isGather16 = attribute.isGather16(this) + def isGather: isGather = attribute.isGather(this) + def isId: isId = attribute.isId(this) + def isIndextype: isIndextype = attribute.isIndextype(this) + def isIota: isIota = attribute.isIota(this) + def isItype: isItype = attribute.isItype(this) + def isLogic: isLogic = attribute.isLogic(this) + def isMa: isMa = attribute.isMa(this) + def isMaskdestination: isMaskdestination = attribute.isMaskdestination(this) + def isMasklogic: isMasklogic = attribute.isMasklogic(this) + def isMasksource: isMasksource = attribute.isMasksource(this) + def isMaskunit: isMaskunit = attribute.isMaskunit(this) + def isMulticycle: isMulticycle = attribute.isMulticycle(this) + def isMultiplier: isMultiplier = attribute.isMultiplier(this) + def isMv: isMv = attribute.isMv(this) + def isNarrow: isNarrow = attribute.isNarrow(this) + def isNr: isNr = attribute.isNr(this) + def isOrderreduce: isOrderreduce = attribute.isOrderreduce(this) + def isOther: isOther = attribute.isOther(this) + def isPopcount: isPopcount = attribute.isPopcount(this) + def isReadonly: isReadonly = attribute.isReadonly(this) + def isRed: isRed = attribute.isRed(this) + def isReverse: isReverse = attribute.isReverse(this) + def isSaturate: isSaturate = attribute.isSaturate(this) + def isScheduler: isScheduler = attribute.isScheduler(this) + def isShift: isShift = attribute.isShift(this) + def isSlid: isSlid = attribute.isSlid(this) + def isSpecial: isSpecial = attribute.isSpecial(this) + def isSpecialslot: isSpecialslot = attribute.isSpecialslot(this) + def isSreadvd: isSreadvd = attribute.isSreadvd(this) + def isSwrite: isSwrite = attribute.isSwrite(this) + def isTargetrd: isTargetrd = attribute.isTargetrd(this) + def isUnorderwrite: isUnorderwrite = attribute.isUnorderwrite(this) + def isUnsigned0: isUnsigned0 = attribute.isUnsigned0(this) + def isUnsigned1: isUnsigned1 = attribute.isUnsigned1(this) + def isVtype: isVtype = attribute.isVtype(this) + def isVwmacc: isVwmacc = attribute.isVwmacc(this) + def isWidenreduce: isWidenreduce = attribute.isWidenreduce(this) private def documentation: String = InstructionDocumentation(instruction, t1Parameter).toString @@ -74,6 +128,60 @@ case class T1DecodePattern(instruction: Instruction, t1Parameter: T1Parameter) e obj.attributesIn :#= Property( Seq( isVector, + isAdder, + isAverage, + isCompress, + isCrossread, + isCrosswrite, + isDivider, + isDontneedexecuteinlane, + isExtend, + isFcompare, + isFfo, + isFirstwiden, + isFloatmul, + isFloat, + isFloattype, + isFma, + isFother, + isGather16, + isGather, + isId, + isIndextype, + isIota, + isItype, + isLogic, + isMa, + isMaskdestination, + isMasklogic, + isMasksource, + isMaskunit, + isMulticycle, + isMultiplier, + isMv, + isNarrow, + isNr, + isOrderreduce, + isOther, + isPopcount, + isReadonly, + isRed, + isReverse, + isSaturate, + isScheduler, + isShift, + isSlid, + isSpecial, + isSpecialslot, + isSreadvd, + isSwrite, + isTargetrd, + isUnorderwrite, + isUnsigned0, + isUnsigned1, + isVtype, + isVwmacc, + isWidenreduce, ).map(_.om.as(attributeClassTpe)) ) obj.getPropertyReference diff --git a/t1/src/decoder/attribute/isAdder.scala b/t1/src/decoder/attribute/isAdder.scala new file mode 100644 index 000000000..1d015e2d3 --- /dev/null +++ b/t1/src/decoder/attribute/isAdder.scala @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isAdder { + def apply(t1DecodePattern: T1DecodePattern): isAdder = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isAdder(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredsum.vs", + "vrsub.vi", + "vrsub.vx", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isAdder(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneAdder]]." +} diff --git a/t1/src/decoder/attribute/isAverage.scala b/t1/src/decoder/attribute/isAverage.scala new file mode 100644 index 000000000..f83a38205 --- /dev/null +++ b/t1/src/decoder/attribute/isAverage.scala @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isAverage { + def apply(t1DecodePattern: T1DecodePattern): isAverage = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isAverage(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isAverage(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "For adder, does it need to take care of saturate. TODO: add to uop " +} diff --git a/t1/src/decoder/attribute/isCompress.scala b/t1/src/decoder/attribute/isCompress.scala new file mode 100644 index 000000000..569c1ea58 --- /dev/null +++ b/t1/src/decoder/attribute/isCompress.scala @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isCompress { + def apply(t1DecodePattern: T1DecodePattern): isCompress = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCompress(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isCompress(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane will read data from vs2, send to Sequencer. then Sequencer will read vs1 for mask. use mask to compress data in vs2. and write to vd at last. " +} diff --git a/t1/src/decoder/attribute/isCrossread.scala b/t1/src/decoder/attribute/isCrossread.scala new file mode 100644 index 000000000..2087647ea --- /dev/null +++ b/t1/src/decoder/attribute/isCrossread.scala @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isCrossread { + def apply(t1DecodePattern: T1DecodePattern): isCrossread = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCrossread(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isCrossread(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "Read vs2 or vd with cross read channel. crossRead -> narrow || firstWiden " +} diff --git a/t1/src/decoder/attribute/isCrosswrite.scala b/t1/src/decoder/attribute/isCrosswrite.scala new file mode 100644 index 000000000..6f3fe2647 --- /dev/null +++ b/t1/src/decoder/attribute/isCrosswrite.scala @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isCrosswrite { + def apply(t1DecodePattern: T1DecodePattern): isCrosswrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isCrosswrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isCrosswrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane should write to another lane" +} diff --git a/t1/src/decoder/attribute/isDivider.scala b/t1/src/decoder/attribute/isDivider.scala new file mode 100644 index 000000000..7417ea2ef --- /dev/null +++ b/t1/src/decoder/attribute/isDivider.scala @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isDivider { + def apply(t1DecodePattern: T1DecodePattern): isDivider = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isDivider(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfdiv.vf", + "vfdiv.vv", + "vfrdiv.vf", + "vfsqrt.v", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isDivider(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneDiv]] or [[org.chipsalliance.t1.rtl.LaneDivFP]]. if FP exist, all div goes to [[org.chipsalliance.t1.rtl.LaneDivFP]]" +} diff --git a/t1/src/decoder/attribute/isDontneedexecuteinlane.scala b/t1/src/decoder/attribute/isDontneedexecuteinlane.scala new file mode 100644 index 000000000..bc61455f9 --- /dev/null +++ b/t1/src/decoder/attribute/isDontneedexecuteinlane.scala @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isDontneedexecuteinlane { + def apply(t1DecodePattern: T1DecodePattern): isDontneedexecuteinlane = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isDontneedexecuteinlane(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "viota.m", + "vl1re16.v", + "vl1re32.v", + "vl1re64.v", + "vl1re8.v", + "vl2re16.v", + "vl2re32.v", + "vl2re64.v", + "vl2re8.v", + "vl4re16.v", + "vl4re32.v", + "vl4re64.v", + "vl4re8.v", + "vl8re16.v", + "vl8re32.v", + "vl8re64.v", + "vl8re8.v", + "vle1024.v", + "vle1024ff.v", + "vle128.v", + "vle128ff.v", + "vle16.v", + "vle16ff.v", + "vle256.v", + "vle256ff.v", + "vle32.v", + "vle32ff.v", + "vle512.v", + "vle512ff.v", + "vle64.v", + "vle64ff.v", + "vle8.v", + "vle8ff.v", + "vlm.v", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vlse1024.v", + "vlse128.v", + "vlse16.v", + "vlse256.v", + "vlse32.v", + "vlse512.v", + "vlse64.v", + "vlse8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vrgather.vv", + "vrgatherei16.vv", + "vs1r.v", + "vs2r.v", + "vs4r.v", + "vs8r.v", + "vse1024.v", + "vse128.v", + "vse16.v", + "vse256.v", + "vse32.v", + "vse512.v", + "vse64.v", + "vse8.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsm.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isDontneedexecuteinlane(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "sExecute 与 wExecuteRes 也不一样,需要校验 sExecute -> readOnly || nr || loadStore Lane doesn't need VFU to execute the instruction. datapath will directly goes to VRF. " +} diff --git a/t1/src/decoder/attribute/isExtend.scala b/t1/src/decoder/attribute/isExtend.scala new file mode 100644 index 000000000..836ce6d88 --- /dev/null +++ b/t1/src/decoder/attribute/isExtend.scala @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isExtend { + def apply(t1DecodePattern: T1DecodePattern): isExtend = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isExtend(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isExtend(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "send element to MaskUnit at top, extend and broadcast to multiple Lanes." +} diff --git a/t1/src/decoder/attribute/isFcompare.scala b/t1/src/decoder/attribute/isFcompare.scala new file mode 100644 index 000000000..299d3f70d --- /dev/null +++ b/t1/src/decoder/attribute/isFcompare.scala @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFcompare { + def apply(t1DecodePattern: T1DecodePattern): isFcompare = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFcompare(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmax.vf", + "vfmax.vv", + "vfmin.vf", + "vfmin.vv", + "vfredmax.vs", + "vfredmin.vs", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFcompare(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove it, but remains attribute." +} diff --git a/t1/src/decoder/attribute/isFfo.scala b/t1/src/decoder/attribute/isFfo.scala new file mode 100644 index 000000000..84cd696a8 --- /dev/null +++ b/t1/src/decoder/attribute/isFfo.scala @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFfo { + def apply(t1DecodePattern: T1DecodePattern): isFfo = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFfo(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfirst.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFfo(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "find first one, lane will report if 1 is found, Sequencer should decide which is exactly the first 1 in lanes. after 1 is found, tell each lane, 1 has been found at which the corresponding location. lane will stale at stage2. TODO: should split into lane control uop " +} diff --git a/t1/src/decoder/attribute/isFirstwiden.scala b/t1/src/decoder/attribute/isFirstwiden.scala new file mode 100644 index 000000000..22482ca21 --- /dev/null +++ b/t1/src/decoder/attribute/isFirstwiden.scala @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFirstwiden { + def apply(t1DecodePattern: T1DecodePattern): isFirstwiden = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFirstwiden(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wv", + "vnsrl.wx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFirstwiden(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "There are two types of widen: - vd -> widen. - vs2, vd -> widen. This op will widen vs2. TODO: remove it as attribute." +} diff --git a/t1/src/decoder/attribute/isFloat.scala b/t1/src/decoder/attribute/isFloat.scala new file mode 100644 index 000000000..8d594894d --- /dev/null +++ b/t1/src/decoder/attribute/isFloat.scala @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFloat { + def apply(t1DecodePattern: T1DecodePattern): isFloat = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloat(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = if(t1DecodePattern.t1Parameter.fpuEnable) Seq( + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + ) else Seq() + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloat(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneFloat]]." +} diff --git a/t1/src/decoder/attribute/isFloatmul.scala b/t1/src/decoder/attribute/isFloatmul.scala new file mode 100644 index 000000000..a9d6001c6 --- /dev/null +++ b/t1/src/decoder/attribute/isFloatmul.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFloatmul { + def apply(t1DecodePattern: T1DecodePattern): isFloatmul = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloatmul(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = if(t1DecodePattern.t1Parameter.fpuEnable) Seq( + "vfmul.vf", + "vfmul.vv", + ) else Seq() + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloatmul(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: add op." +} diff --git a/t1/src/decoder/attribute/isFloattype.scala b/t1/src/decoder/attribute/isFloattype.scala new file mode 100644 index 000000000..4ef677661 --- /dev/null +++ b/t1/src/decoder/attribute/isFloattype.scala @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFloattype { + def apply(t1DecodePattern: T1DecodePattern): isFloattype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFloattype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = if(t1DecodePattern.t1Parameter.fpuEnable) Seq( + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + ) else Seq() + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFloattype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "is a float type. TODO: remove it." +} diff --git a/t1/src/decoder/attribute/isFma.scala b/t1/src/decoder/attribute/isFma.scala new file mode 100644 index 000000000..5144fee70 --- /dev/null +++ b/t1/src/decoder/attribute/isFma.scala @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFma { + def apply(t1DecodePattern: T1DecodePattern): isFma = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFma(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfadd.vf", + "vfadd.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfredosum.vs", + "vfredusum.vs", + "vfrsub.vf", + "vfsub.vf", + "vfsub.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFma(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "uop of FMA, goes to [[org.chipsalliance.t1.rtl.LaneFloat]] FMA unit." +} diff --git a/t1/src/decoder/attribute/isFother.scala b/t1/src/decoder/attribute/isFother.scala new file mode 100644 index 000000000..211bd5d16 --- /dev/null +++ b/t1/src/decoder/attribute/isFother.scala @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isFother { + def apply(t1DecodePattern: T1DecodePattern): isFother = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isFother(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfrec7.v", + "vfrsqrt7.v", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isFother(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "designed for Other Unit in FP. goes to [[org.chipsalliance.t1.rtl.LaneFloat]] OtherUnit. TODO: perf it." +} diff --git a/t1/src/decoder/attribute/isGather.scala b/t1/src/decoder/attribute/isGather.scala new file mode 100644 index 000000000..72b047bb4 --- /dev/null +++ b/t1/src/decoder/attribute/isGather.scala @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isGather { + def apply(t1DecodePattern: T1DecodePattern): isGather = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isGather(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isGather(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane will read index from vs1, send to Sequencer. mask unit will calculate vrf address based on the vs1 from lane, and send read request to lanes, lanes should read it and send vs2 to Sequencer. Sequencer will write vd at last. address: 0 -> vlmax(sew decide address width.) " +} diff --git a/t1/src/decoder/attribute/isGather16.scala b/t1/src/decoder/attribute/isGather16.scala new file mode 100644 index 000000000..fa115d4c8 --- /dev/null +++ b/t1/src/decoder/attribute/isGather16.scala @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isGather16 { + def apply(t1DecodePattern: T1DecodePattern): isGather16 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isGather16(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrgatherei16.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isGather16(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "same with [[gather]] ignore sew, address width is fixed to 16. @note When SEW=8, vrgather.vv can only reference vector elements 0-255. The vrgatherei16 form can index 64K elements, and can also be used to reduce the register capacity needed to hold indices when SEW > 16. " +} diff --git a/t1/src/decoder/attribute/isId.scala b/t1/src/decoder/attribute/isId.scala new file mode 100644 index 000000000..ec0884b18 --- /dev/null +++ b/t1/src/decoder/attribute/isId.scala @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isId { + def apply(t1DecodePattern: T1DecodePattern): isId = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isId(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfdiv.vf", + "vfdiv.vv", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrdiv.vf", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wv", + "vnsrl.wx", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.wv", + "vwsub.wx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isId(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "write 0...vlmax to VRF. Lane other unit should handle it. TODO: remove it, it's a uop. " +} diff --git a/t1/src/decoder/attribute/isIndextype.scala b/t1/src/decoder/attribute/isIndextype.scala new file mode 100644 index 000000000..064ada661 --- /dev/null +++ b/t1/src/decoder/attribute/isIndextype.scala @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isIndextype { + def apply(t1DecodePattern: T1DecodePattern): isIndextype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isIndextype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isIndextype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove it." +} diff --git a/t1/src/decoder/attribute/isIota.scala b/t1/src/decoder/attribute/isIota.scala new file mode 100644 index 000000000..467d0a95c --- /dev/null +++ b/t1/src/decoder/attribute/isIota.scala @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isIota { + def apply(t1DecodePattern: T1DecodePattern): isIota = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isIota(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "viota.m", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isIota(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane will read vs2 from VRF, send to Top. Top read v0(at register) calculate the result and write back to VRFs " +} diff --git a/t1/src/decoder/attribute/isItype.scala b/t1/src/decoder/attribute/isItype.scala new file mode 100644 index 000000000..3901ecd3e --- /dev/null +++ b/t1/src/decoder/attribute/isItype.scala @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isItype { + def apply(t1DecodePattern: T1DecodePattern): isItype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isItype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadd.vi", + "vand.vi", + "vmadc.vi", + "vmadc.vim", + "vmerge.vim", + "vmseq.vi", + "vmsgt.vi", + "vmsgtu.vi", + "vmsle.vi", + "vmsleu.vi", + "vmsne.vi", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vnclip.wi", + "vnclipu.wi", + "vnsra.wi", + "vnsrl.wi", + "vor.vi", + "vrgather.vi", + "vrsub.vi", + "vsadd.vi", + "vsaddu.vi", + "vslidedown.vi", + "vslideup.vi", + "vsll.vi", + "vsra.vi", + "vsrl.vi", + "vssra.vi", + "vssrl.vi", + "vxor.vi", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isItype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "src is imm." +} diff --git a/t1/src/decoder/attribute/isLogic.scala b/t1/src/decoder/attribute/isLogic.scala new file mode 100644 index 000000000..34f019b45 --- /dev/null +++ b/t1/src/decoder/attribute/isLogic.scala @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isLogic { + def apply(t1DecodePattern: T1DecodePattern): isLogic = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isLogic(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vand.vi", + "vand.vv", + "vand.vx", + "vmand.mm", + "vmandn.mm", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmxnor.mm", + "vmxor.mm", + "vor.vi", + "vor.vv", + "vor.vx", + "vredand.vs", + "vredor.vs", + "vredxor.vs", + "vxor.vi", + "vxor.vv", + "vxor.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isLogic(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "Instruction should use [[org.chipsalliance.t1.rtl.decoder.TableGenerator.LaneDecodeTable.LogicUnit]]." +} diff --git a/t1/src/decoder/attribute/isMa.scala b/t1/src/decoder/attribute/isMa.scala new file mode 100644 index 000000000..c114290f0 --- /dev/null +++ b/t1/src/decoder/attribute/isMa.scala @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMa { + def apply(t1DecodePattern: T1DecodePattern): isMa = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMa(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vcompress.vm", + "vcpop.m", + "vfirst.m", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "viota.m", + "vmacc.vv", + "vmacc.vx", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmadd.vv", + "vmadd.vx", + "vmand.mm", + "vmandn.mm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vmxnor.mm", + "vmxor.mm", + "vnmsac.vv", + "vnmsac.vx", + "vnmsub.vv", + "vnmsub.vx", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrgather.vv", + "vrgatherei16.vv", + "vsbc.vvm", + "vsbc.vxm", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMa(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "decodeResult(Decoder.multiplier) && decodeResult(Decoder.uop)(1, 0).xorR && !decodeResult(Decoder.vwmacc) TODO: remove it. */ " +} diff --git a/t1/src/decoder/attribute/isMaskdestination.scala b/t1/src/decoder/attribute/isMaskdestination.scala new file mode 100644 index 000000000..0016761ae --- /dev/null +++ b/t1/src/decoder/attribute/isMaskdestination.scala @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMaskdestination { + def apply(t1DecodePattern: T1DecodePattern): isMaskdestination = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMaskdestination(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMaskdestination(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "vd is mask format. execute at lane, send result to Sequencer, regroup it and write to vd. if datapath is unaligned, need to take care the tail. " +} diff --git a/t1/src/decoder/attribute/isMasklogic.scala b/t1/src/decoder/attribute/isMasklogic.scala new file mode 100644 index 000000000..bc0dc53cf --- /dev/null +++ b/t1/src/decoder/attribute/isMasklogic.scala @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMasklogic { + def apply(t1DecodePattern: T1DecodePattern): isMasklogic = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMasklogic(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "viota.m", + "vmand.mm", + "vmandn.mm", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmxnor.mm", + "vmxor.mm", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMasklogic(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "only one or two operators src is mask format(one element one bit). vl should align with src. if datapath is unaligned, need to take care the tail. " +} diff --git a/t1/src/decoder/attribute/isMasksource.scala b/t1/src/decoder/attribute/isMasksource.scala new file mode 100644 index 000000000..105053536 --- /dev/null +++ b/t1/src/decoder/attribute/isMasksource.scala @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMasksource { + def apply(t1DecodePattern: T1DecodePattern): isMasksource = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMasksource(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vfmerge.vfm", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vsbc.vvm", + "vsbc.vxm", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMasksource(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "three ops. these ops don't use mask. use v0 as third op, read it from duplicate V0. it will read use mask(v0) in mask format as source. " +} diff --git a/t1/src/decoder/attribute/isMaskunit.scala b/t1/src/decoder/attribute/isMaskunit.scala new file mode 100644 index 000000000..4e0f4b0c3 --- /dev/null +++ b/t1/src/decoder/attribute/isMaskunit.scala @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMaskunit { + def apply(t1DecodePattern: T1DecodePattern): isMaskunit = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMaskunit(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "vfwredosum.vs", + "vfwredusum.vs", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrgather.vv", + "vrgatherei16.vv", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMaskunit(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "mask unit -> red || compress || viota || ffo || slid || maskDestination || gather(v) || mv || popCount || extend all instruction in Sequencer mask unit. " +} diff --git a/t1/src/decoder/attribute/isMulticycle.scala b/t1/src/decoder/attribute/isMulticycle.scala new file mode 100644 index 000000000..a17e2839f --- /dev/null +++ b/t1/src/decoder/attribute/isMulticycle.scala @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMulticycle { + def apply(t1DecodePattern: T1DecodePattern): isMulticycle = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMulticycle(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMulticycle(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "TODO: remove? only Div or customer" +} diff --git a/t1/src/decoder/attribute/isMultiplier.scala b/t1/src/decoder/attribute/isMultiplier.scala new file mode 100644 index 000000000..4595c7845 --- /dev/null +++ b/t1/src/decoder/attribute/isMultiplier.scala @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMultiplier { + def apply(t1DecodePattern: T1DecodePattern): isMultiplier = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMultiplier(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmacc.vv", + "vmacc.vx", + "vmadd.vv", + "vmadd.vx", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vnmsac.vv", + "vnmsac.vx", + "vnmsub.vv", + "vnmsub.vx", + "vsmul.vv", + "vsmul.vx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMultiplier(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneMul]]. (only apply to int mul)" +} diff --git a/t1/src/decoder/attribute/isMv.scala b/t1/src/decoder/attribute/isMv.scala new file mode 100644 index 000000000..3f0c2315e --- /dev/null +++ b/t1/src/decoder/attribute/isMv.scala @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isMv { + def apply(t1DecodePattern: T1DecodePattern): isMv = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isMv(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmv.f.s", + "vfmv.s.f", + "vmv.s.x", + "vmv.x.s", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isMv(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "move instruction, v->v s->v x->v, single element move. TODO: split them into multiple op since datapath differs " +} diff --git a/t1/src/decoder/attribute/isNarrow.scala b/t1/src/decoder/attribute/isNarrow.scala new file mode 100644 index 000000000..e00ce6524 --- /dev/null +++ b/t1/src/decoder/attribute/isNarrow.scala @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isNarrow { + def apply(t1DecodePattern: T1DecodePattern): isNarrow = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isNarrow(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isNarrow(value: TriState) extends BooleanDecodeAttribute { + override val description: String = " dual width of src will be convert to single width to dst. narrow can be the src of chain. as the dst of chain, only can be fed with Load. TODO: remove it as attribute. " +} diff --git a/t1/src/decoder/attribute/isNr.scala b/t1/src/decoder/attribute/isNr.scala new file mode 100644 index 000000000..279c1f232 --- /dev/null +++ b/t1/src/decoder/attribute/isNr.scala @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isNr { + def apply(t1DecodePattern: T1DecodePattern): isNr = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isNr(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isNr(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "for vmvnr, move vreg group to another vreg group. it will ignore lmul, use from instr. chainable" +} diff --git a/t1/src/decoder/attribute/isOrderreduce.scala b/t1/src/decoder/attribute/isOrderreduce.scala new file mode 100644 index 000000000..347c74078 --- /dev/null +++ b/t1/src/decoder/attribute/isOrderreduce.scala @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isOrderreduce { + def apply(t1DecodePattern: T1DecodePattern): isOrderreduce = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isOrderreduce(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfredosum.vs", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isOrderreduce(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "don't use it, it's slow, lane read all elements from VRF, send to Top." +} diff --git a/t1/src/decoder/attribute/isOther.scala b/t1/src/decoder/attribute/isOther.scala new file mode 100644 index 000000000..db76a5da9 --- /dev/null +++ b/t1/src/decoder/attribute/isOther.scala @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isOther { + def apply(t1DecodePattern: T1DecodePattern): isOther = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isOther(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "vfmerge.vfm", + "vfmv.s.f", + "vid.v", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isOther(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.OtherUnit]]" +} diff --git a/t1/src/decoder/attribute/isPopcount.scala b/t1/src/decoder/attribute/isPopcount.scala new file mode 100644 index 000000000..f8671544b --- /dev/null +++ b/t1/src/decoder/attribute/isPopcount.scala @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isPopcount { + def apply(t1DecodePattern: T1DecodePattern): isPopcount = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isPopcount(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isPopcount(value: TriState) extends BooleanDecodeAttribute { + override val description: String = " count how many 1s in VS2. lane will use [[org.chipsalliance.t1.rtl.OtherUnit]] to how many 1s locally; use reduce datapath to accumulate, send total result to top top will send result to vd. " +} diff --git a/t1/src/decoder/attribute/isReadonly.scala b/t1/src/decoder/attribute/isReadonly.scala new file mode 100644 index 000000000..089578c09 --- /dev/null +++ b/t1/src/decoder/attribute/isReadonly.scala @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isReadonly { + def apply(t1DecodePattern: T1DecodePattern): isReadonly = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isReadonly(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "viota.m", + "vrgather.vv", + "vrgatherei16.vv", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isReadonly(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane read only instructions. for these instructions lane will only read vrf and send data back to Sequencer. " +} diff --git a/t1/src/decoder/attribute/isRed.scala b/t1/src/decoder/attribute/isRed.scala new file mode 100644 index 000000000..8f40f1ef2 --- /dev/null +++ b/t1/src/decoder/attribute/isRed.scala @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isRed { + def apply(t1DecodePattern: T1DecodePattern): isRed = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isRed(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfwredosum.vs", + "vfwredusum.vs", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vwredsum.vs", + "vwredsumu.vs", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isRed(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "do reduce in each lane. each element will sequentially executed in each lanes. after finishing, pop it to Top, and use ALU at top to get the final result and send to element0 TODO: better name. " +} diff --git a/t1/src/decoder/attribute/isReverse.scala b/t1/src/decoder/attribute/isReverse.scala new file mode 100644 index 000000000..729976ae9 --- /dev/null +++ b/t1/src/decoder/attribute/isReverse.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isReverse { + def apply(t1DecodePattern: T1DecodePattern): isReverse = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isReverse(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vrsub.vi", + "vrsub.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isReverse(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "only instruction will switch src. TODO: send it to uop. " +} diff --git a/t1/src/decoder/attribute/isSaturate.scala b/t1/src/decoder/attribute/isSaturate.scala new file mode 100644 index 000000000..4b309d26a --- /dev/null +++ b/t1/src/decoder/attribute/isSaturate.scala @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSaturate { + def apply(t1DecodePattern: T1DecodePattern): isSaturate = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSaturate(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsm.v", + "vsmul.vv", + "vsmul.vx", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSaturate(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "For adder, does it need to take care of saturate. TODO: add to uop " +} diff --git a/t1/src/decoder/attribute/isScheduler.scala b/t1/src/decoder/attribute/isScheduler.scala new file mode 100644 index 000000000..b26150800 --- /dev/null +++ b/t1/src/decoder/attribute/isScheduler.scala @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isScheduler { + def apply(t1DecodePattern: T1DecodePattern): isScheduler = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isScheduler(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vand.vi", + "vand.vv", + "vand.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmacc.vf", + "vfmacc.vv", + "vfmadd.vf", + "vfmadd.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmin.vf", + "vfmin.vv", + "vfmsac.vf", + "vfmsac.vv", + "vfmsub.vf", + "vfmsub.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vf", + "vfnmacc.vv", + "vfnmadd.vf", + "vfnmadd.vv", + "vfnmsac.vf", + "vfnmsac.vv", + "vfnmsub.vf", + "vfnmsub.vv", + "vfrdiv.vf", + "vfrec7.v", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vmacc.vv", + "vmacc.vx", + "vmadd.vv", + "vmadd.vx", + "vmand.mm", + "vmandn.mm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnmsac.vv", + "vnmsac.vx", + "vnmsub.vv", + "vnmsub.vx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vor.vi", + "vor.vv", + "vor.vx", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vrgather.vi", + "vrgather.vx", + "vrsub.vi", + "vrsub.vx", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsmul.vv", + "vsmul.vx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vxor.vi", + "vxor.vv", + "vxor.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isScheduler(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "wScheduler 原来与 sScheduler 如果出错了需要检查一下,真不一样需要说明记录 sScheduler -> maskDestination || red || readOnly || ffo || popCount || loadStore lane will send request to Sequencer and wait ack from Sequencer. */ " +} diff --git a/t1/src/decoder/attribute/isShift.scala b/t1/src/decoder/attribute/isShift.scala new file mode 100644 index 000000000..06723d375 --- /dev/null +++ b/t1/src/decoder/attribute/isShift.scala @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isShift { + def apply(t1DecodePattern: T1DecodePattern): isShift = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isShift(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isShift(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.LaneShifter]]." +} diff --git a/t1/src/decoder/attribute/isSlid.scala b/t1/src/decoder/attribute/isSlid.scala new file mode 100644 index 000000000..8ae73d9b0 --- /dev/null +++ b/t1/src/decoder/attribute/isSlid.scala @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSlid { + def apply(t1DecodePattern: T1DecodePattern): isSlid = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSlid(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfslide1down.vf", + "vfslide1up.vf", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSlid(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "used in Sequencer mask unit, decide which vrf should be read. send read request to corresponding lane, lane will respond data to Sequencer. Sequencer will write data to VD. mask unit is work as the router here. TODO: opimize mask unit. " +} diff --git a/t1/src/decoder/attribute/isSpecial.scala b/t1/src/decoder/attribute/isSpecial.scala new file mode 100644 index 000000000..ba0ad24c3 --- /dev/null +++ b/t1/src/decoder/attribute/isSpecial.scala @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSpecial { + def apply(t1DecodePattern: T1DecodePattern): isSpecial = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSpecial(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vcompress.vm", + "vcpop.m", + "vfirst.m", + "vfmerge.vfm", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "vfwadd.wf", + "vfwadd.wv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.wf", + "vfwsub.wv", + "viota.m", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmand.mm", + "vmandn.mm", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrgather.vv", + "vrgatherei16.vv", + "vsbc.vvm", + "vsbc.vxm", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSpecial(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "if Sequencer is the router for data from Lane to LSU or Sequencer mask unit. special -> maskUnit || index type load store " +} diff --git a/t1/src/decoder/attribute/isSpecialslot.scala b/t1/src/decoder/attribute/isSpecialslot.scala new file mode 100644 index 000000000..7d830f8c8 --- /dev/null +++ b/t1/src/decoder/attribute/isSpecialslot.scala @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSpecialslot { + def apply(t1DecodePattern: T1DecodePattern): isSpecialslot = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSpecialslot(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vcpop.m", + "vfirst.m", + "vfmerge.vfm", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfwadd.wf", + "vfwadd.wv", + "vfwsub.wf", + "vfwsub.wv", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmand.mm", + "vmandn.mm", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmsof.m", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vsbc.vvm", + "vsbc.vxm", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSpecialslot(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "lane中只能在slot0中执行的指令 specialSlot -> crossRead || crossWrite || maskLogic || maskDestination || maskSource instructions schedule to slot0. " +} diff --git a/t1/src/decoder/attribute/isSreadvd.scala b/t1/src/decoder/attribute/isSreadvd.scala new file mode 100644 index 000000000..76c176c17 --- /dev/null +++ b/t1/src/decoder/attribute/isSreadvd.scala @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSreadvd { + def apply(t1DecodePattern: T1DecodePattern): isSreadvd = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSreadvd(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaadd.vx", + "vaaddu.vv", + "vaaddu.vx", + "vadc.vim", + "vadc.vvm", + "vadc.vxm", + "vadd.vi", + "vadd.vv", + "vadd.vx", + "vand.vi", + "vand.vv", + "vand.vx", + "vasub.vv", + "vasub.vx", + "vasubu.vv", + "vasubu.vx", + "vcompress.vm", + "vdiv.vv", + "vdiv.vx", + "vdivu.vv", + "vdivu.vx", + "vfadd.vf", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vf", + "vfdiv.vv", + "vfmax.vf", + "vfmax.vv", + "vfmerge.vfm", + "vfmin.vf", + "vfmin.vv", + "vfmul.vf", + "vfmul.vv", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrdiv.vf", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfrsub.vf", + "vfsgnj.vf", + "vfsgnj.vv", + "vfsgnjn.vf", + "vfsgnjn.vv", + "vfsgnjx.vf", + "vfsgnjx.vv", + "vfslide1down.vf", + "vfslide1up.vf", + "vfsqrt.v", + "vfsub.vf", + "vfsub.vv", + "vfwadd.vf", + "vfwadd.vv", + "vfwadd.wf", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vf", + "vfwmacc.vv", + "vfwmsac.vf", + "vfwmsac.vv", + "vfwmul.vf", + "vfwmul.vv", + "vfwnmacc.vf", + "vfwnmacc.vv", + "vfwnmsac.vf", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vf", + "vfwsub.vv", + "vfwsub.wf", + "vfwsub.wv", + "vid.v", + "vl1re16.v", + "vl1re32.v", + "vl1re64.v", + "vl1re8.v", + "vl2re16.v", + "vl2re32.v", + "vl2re64.v", + "vl2re8.v", + "vl4re16.v", + "vl4re32.v", + "vl4re64.v", + "vl4re8.v", + "vl8re16.v", + "vl8re32.v", + "vl8re64.v", + "vl8re8.v", + "vle1024.v", + "vle1024ff.v", + "vle128.v", + "vle128ff.v", + "vle16.v", + "vle16ff.v", + "vle256.v", + "vle256ff.v", + "vle32.v", + "vle32ff.v", + "vle512.v", + "vle512ff.v", + "vle64.v", + "vle64ff.v", + "vle8.v", + "vle8ff.v", + "vlm.v", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vlse1024.v", + "vlse128.v", + "vlse16.v", + "vlse256.v", + "vlse32.v", + "vlse512.v", + "vlse64.v", + "vlse8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmax.vv", + "vmax.vx", + "vmaxu.vv", + "vmaxu.vx", + "vmerge.vim", + "vmerge.vvm", + "vmerge.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmin.vv", + "vmin.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmul.vv", + "vmul.vx", + "vmulh.vv", + "vmulh.vx", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vnclip.wi", + "vnclip.wv", + "vnclip.wx", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsra.wi", + "vnsra.wv", + "vnsra.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vor.vi", + "vor.vv", + "vor.vx", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrem.vv", + "vrem.vx", + "vremu.vv", + "vremu.vx", + "vrgather.vi", + "vrgather.vv", + "vrgather.vx", + "vrgatherei16.vv", + "vrsub.vi", + "vrsub.vx", + "vs1r.v", + "vs2r.v", + "vs4r.v", + "vs8r.v", + "vsadd.vi", + "vsadd.vv", + "vsadd.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsbc.vvm", + "vsbc.vxm", + "vse1024.v", + "vse128.v", + "vse16.v", + "vse256.v", + "vse32.v", + "vse512.v", + "vse64.v", + "vse8.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsm.v", + "vsmul.vv", + "vsmul.vx", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsra.vi", + "vsra.vv", + "vsra.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vssra.vi", + "vssra.vv", + "vssra.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssub.vv", + "vssub.vx", + "vssubu.vv", + "vssubu.vx", + "vsub.vv", + "vsub.vx", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vxor.vi", + "vxor.vv", + "vxor.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSreadvd(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "sReadVD -> !(ma || maskLogic) instruction need to read vd as operator. " +} diff --git a/t1/src/decoder/attribute/isSwrite.scala b/t1/src/decoder/attribute/isSwrite.scala new file mode 100644 index 000000000..228d2297d --- /dev/null +++ b/t1/src/decoder/attribute/isSwrite.scala @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isSwrite { + def apply(t1DecodePattern: T1DecodePattern): isSwrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isSwrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfwredosum.vs", + "vfwredusum.vs", + "viota.m", + "vl1re16.v", + "vl1re32.v", + "vl1re64.v", + "vl1re8.v", + "vl2re16.v", + "vl2re32.v", + "vl2re64.v", + "vl2re8.v", + "vl4re16.v", + "vl4re32.v", + "vl4re64.v", + "vl4re8.v", + "vl8re16.v", + "vl8re32.v", + "vl8re64.v", + "vl8re8.v", + "vle1024.v", + "vle1024ff.v", + "vle128.v", + "vle128ff.v", + "vle16.v", + "vle16ff.v", + "vle256.v", + "vle256ff.v", + "vle32.v", + "vle32ff.v", + "vle512.v", + "vle512ff.v", + "vle64.v", + "vle64ff.v", + "vle8.v", + "vle8ff.v", + "vlm.v", + "vloxei1024.v", + "vloxei128.v", + "vloxei16.v", + "vloxei256.v", + "vloxei32.v", + "vloxei512.v", + "vloxei64.v", + "vloxei8.v", + "vlse1024.v", + "vlse128.v", + "vlse16.v", + "vlse256.v", + "vlse32.v", + "vlse512.v", + "vlse64.v", + "vlse8.v", + "vluxei1024.v", + "vluxei128.v", + "vluxei16.v", + "vluxei256.v", + "vluxei32.v", + "vluxei512.v", + "vluxei64.v", + "vluxei8.v", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmfeq.vf", + "vmfeq.vv", + "vmfge.vf", + "vmfgt.vf", + "vmfle.vf", + "vmfle.vv", + "vmflt.vf", + "vmflt.vv", + "vmfne.vf", + "vmfne.vv", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmseq.vi", + "vmseq.vv", + "vmseq.vx", + "vmsgt.vi", + "vmsgt.vx", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsle.vi", + "vmsle.vv", + "vmsle.vx", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmslt.vv", + "vmslt.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsne.vi", + "vmsne.vv", + "vmsne.vx", + "vmv.x.s", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrgather.vv", + "vrgatherei16.vv", + "vs1r.v", + "vs2r.v", + "vs4r.v", + "vs8r.v", + "vse1024.v", + "vse128.v", + "vse16.v", + "vse256.v", + "vse32.v", + "vse512.v", + "vse64.v", + "vse8.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsm.v", + "vsoxei1024.v", + "vsoxei128.v", + "vsoxei16.v", + "vsoxei256.v", + "vsoxei32.v", + "vsoxei512.v", + "vsoxei64.v", + "vsoxei8.v", + "vsse1024.v", + "vsse128.v", + "vsse16.v", + "vsse256.v", + "vsse32.v", + "vsse512.v", + "vsse64.v", + "vsse8.v", + "vsuxei1024.v", + "vsuxei128.v", + "vsuxei16.v", + "vsuxei256.v", + "vsuxei32.v", + "vsuxei512.v", + "vsuxei64.v", + "vsuxei8.v", + "vwadd.vv", + "vwadd.vx", + "vwadd.wv", + "vwadd.wx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmul.vv", + "vwmul.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.vx", + "vwsub.wv", + "vwsub.wx", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isSwrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "sWrite -> targetRd || readOnly || crossWrite || maskDestination || reduce || loadStore instruction will write vd or rd(scalar) from outside of lane. It will request vrf wait, and lane will not write. " +} diff --git a/t1/src/decoder/attribute/isTargetrd.scala b/t1/src/decoder/attribute/isTargetrd.scala new file mode 100644 index 000000000..bd01c44ed --- /dev/null +++ b/t1/src/decoder/attribute/isTargetrd.scala @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isTargetrd { + def apply(t1DecodePattern: T1DecodePattern): isTargetrd = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isTargetrd(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfirst.m", + "vfmv.f.s", + "vmv.x.s", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isTargetrd(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "write rd/fd at scalar core." +} diff --git a/t1/src/decoder/attribute/isUnorderwrite.scala b/t1/src/decoder/attribute/isUnorderwrite.scala new file mode 100644 index 000000000..d8f662b7b --- /dev/null +++ b/t1/src/decoder/attribute/isUnorderwrite.scala @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isUnorderwrite { + def apply(t1DecodePattern: T1DecodePattern): isUnorderwrite = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnorderwrite(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vfmv.f.s", + "vfmv.s.f", + "vfredosum.vs", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv.s.x", + "vmv.x.s", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnorderwrite(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "unmanaged write for VRF. these instructions cannot be chain as source. TODO: add an attribute these instruction cannot be the source of chaining. " +} diff --git a/t1/src/decoder/attribute/isUnsigned0.scala b/t1/src/decoder/attribute/isUnsigned0.scala new file mode 100644 index 000000000..273f806b4 --- /dev/null +++ b/t1/src/decoder/attribute/isUnsigned0.scala @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isUnsigned0 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned0 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnsigned0(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaaddu.vv", + "vaaddu.vx", + "vasubu.vv", + "vasubu.vx", + "vcpop.m", + "vdivu.vv", + "vdivu.vx", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmaxu.vv", + "vmaxu.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsof.m", + "vmulhsu.vv", + "vmulhsu.vx", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vredmaxu.vs", + "vredminu.vs", + "vremu.vv", + "vremu.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssubu.vv", + "vssubu.vx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + "vwmulsu.vv", + "vwmulsu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsumu.vs", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnsigned0(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "is src0 unsigned? used everywhere in Lane and VFU. " +} diff --git a/t1/src/decoder/attribute/isUnsigned1.scala b/t1/src/decoder/attribute/isUnsigned1.scala new file mode 100644 index 000000000..54d30d3d0 --- /dev/null +++ b/t1/src/decoder/attribute/isUnsigned1.scala @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isUnsigned1 { + def apply(t1DecodePattern: T1DecodePattern): isUnsigned1 = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isUnsigned1(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaaddu.vv", + "vaaddu.vx", + "vasubu.vv", + "vasubu.vx", + "vcpop.m", + "vdivu.vv", + "vdivu.vx", + "vfcvt.f.xu.v", + "vfcvt.rtz.xu.f.v", + "vfirst.m", + "vid.v", + "viota.m", + "vmadc.vi", + "vmadc.vim", + "vmadc.vv", + "vmadc.vvm", + "vmadc.vx", + "vmadc.vxm", + "vmaxu.vv", + "vmaxu.vx", + "vminu.vv", + "vminu.vx", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbc.vx", + "vmsbc.vxm", + "vmsbf.m", + "vmsgtu.vi", + "vmsgtu.vx", + "vmsif.m", + "vmsleu.vi", + "vmsleu.vv", + "vmsleu.vx", + "vmsltu.vv", + "vmsltu.vx", + "vmsof.m", + "vmulhu.vv", + "vmulhu.vx", + "vmv.s.x", + "vmv.x.s", + "vnclipu.wi", + "vnclipu.wv", + "vnclipu.wx", + "vnsrl.wi", + "vnsrl.wv", + "vnsrl.wx", + "vredmaxu.vs", + "vredminu.vs", + "vremu.vv", + "vremu.vx", + "vsaddu.vi", + "vsaddu.vv", + "vsaddu.vx", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsll.vi", + "vsll.vv", + "vsll.vx", + "vsrl.vi", + "vsrl.vv", + "vsrl.vx", + "vssrl.vi", + "vssrl.vv", + "vssrl.vx", + "vssubu.vv", + "vssubu.vx", + "vwaddu.vv", + "vwaddu.vx", + "vwaddu.wv", + "vwaddu.wx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmulu.vv", + "vwmulu.vx", + "vwredsumu.vs", + "vwsubu.vv", + "vwsubu.vx", + "vwsubu.wv", + "vwsubu.wx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isUnsigned1(value: TriState) extends BooleanDecodeAttribute { + override val description: String = " is src1 unsigned? used everywhere in Lane and VFU. " +} diff --git a/t1/src/decoder/attribute/isVtype.scala b/t1/src/decoder/attribute/isVtype.scala new file mode 100644 index 000000000..a0e7c2746 --- /dev/null +++ b/t1/src/decoder/attribute/isVtype.scala @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isVtype { + def apply(t1DecodePattern: T1DecodePattern): isVtype = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isVtype(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vaadd.vv", + "vaaddu.vv", + "vadc.vvm", + "vadd.vv", + "vand.vv", + "vasub.vv", + "vasubu.vv", + "vcompress.vm", + "vcpop.m", + "vdiv.vv", + "vdivu.vv", + "vfadd.vv", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfdiv.vv", + "vfirst.m", + "vfmacc.vv", + "vfmadd.vv", + "vfmax.vv", + "vfmin.vv", + "vfmsac.vv", + "vfmsub.vv", + "vfmul.vv", + "vfmv.f.s", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfnmacc.vv", + "vfnmadd.vv", + "vfnmsac.vv", + "vfnmsub.vv", + "vfrec7.v", + "vfredmax.vs", + "vfredmin.vs", + "vfredosum.vs", + "vfredusum.vs", + "vfrsqrt7.v", + "vfsgnj.vv", + "vfsgnjn.vv", + "vfsgnjx.vv", + "vfsqrt.v", + "vfsub.vv", + "vfwadd.vv", + "vfwadd.wv", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vfwmacc.vv", + "vfwmsac.vv", + "vfwmul.vv", + "vfwnmacc.vv", + "vfwnmsac.vv", + "vfwredosum.vs", + "vfwredusum.vs", + "vfwsub.vv", + "vfwsub.wv", + "vid.v", + "viota.m", + "vmacc.vv", + "vmadc.vv", + "vmadc.vvm", + "vmadd.vv", + "vmand.mm", + "vmandn.mm", + "vmax.vv", + "vmaxu.vv", + "vmerge.vvm", + "vmfeq.vv", + "vmfle.vv", + "vmflt.vv", + "vmfne.vv", + "vmin.vv", + "vminu.vv", + "vmnand.mm", + "vmnor.mm", + "vmor.mm", + "vmorn.mm", + "vmsbc.vv", + "vmsbc.vvm", + "vmsbf.m", + "vmseq.vv", + "vmsif.m", + "vmsle.vv", + "vmsleu.vv", + "vmslt.vv", + "vmsltu.vv", + "vmsne.vv", + "vmsof.m", + "vmul.vv", + "vmulh.vv", + "vmulhsu.vv", + "vmulhu.vv", + "vmv.x.s", + "vmxnor.mm", + "vmxor.mm", + "vnclip.wv", + "vnclipu.wv", + "vnmsac.vv", + "vnmsub.vv", + "vnsra.wv", + "vnsrl.wv", + "vor.vv", + "vredand.vs", + "vredmax.vs", + "vredmaxu.vs", + "vredmin.vs", + "vredminu.vs", + "vredor.vs", + "vredsum.vs", + "vredxor.vs", + "vrem.vv", + "vremu.vv", + "vrgather.vv", + "vrgatherei16.vv", + "vsadd.vv", + "vsaddu.vv", + "vsbc.vvm", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vsll.vv", + "vsmul.vv", + "vsra.vv", + "vsrl.vv", + "vssra.vv", + "vssrl.vv", + "vssub.vv", + "vssubu.vv", + "vsub.vv", + "vwadd.vv", + "vwadd.wv", + "vwaddu.vv", + "vwaddu.wv", + "vwmacc.vv", + "vwmaccsu.vv", + "vwmaccu.vv", + "vwmul.vv", + "vwmulsu.vv", + "vwmulu.vv", + "vwredsum.vs", + "vwredsumu.vs", + "vwsub.vv", + "vwsub.wv", + "vwsubu.vv", + "vwsubu.wv", + "vxor.vv", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isVtype(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "src1 is vtype." +} diff --git a/t1/src/decoder/attribute/isVwmacc.scala b/t1/src/decoder/attribute/isVwmacc.scala new file mode 100644 index 000000000..957c6b619 --- /dev/null +++ b/t1/src/decoder/attribute/isVwmacc.scala @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isVwmacc { + def apply(t1DecodePattern: T1DecodePattern): isVwmacc = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isVwmacc(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwmacc.vv", + "vwmacc.vx", + "vwmaccsu.vv", + "vwmaccsu.vx", + "vwmaccu.vv", + "vwmaccu.vx", + "vwmaccus.vx", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isVwmacc(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "special MAC instruction, MAC use vd as source, it cross read vd. TODO: cross read vd + mac uop. " +} diff --git a/t1/src/decoder/attribute/isWidenreduce.scala b/t1/src/decoder/attribute/isWidenreduce.scala new file mode 100644 index 000000000..58c39fe00 --- /dev/null +++ b/t1/src/decoder/attribute/isWidenreduce.scala @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isWidenreduce { + def apply(t1DecodePattern: T1DecodePattern): isWidenreduce = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isWidenreduce(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vwredsum.vs", + "vwredsumu.vs", + ) + allMatched.contains(t1DecodePattern.instruction) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.t1Parameter.allInstuctions.filter( i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isWidenreduce(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "a special widen, only write dual vd from Top to element0 it doesn't cross. TODO: better name. " +}