From 93fcb10fdb472e8b321caaaf71642a64abe84c2b Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 26 Dec 2024 13:06:39 +0800 Subject: [PATCH] [rtl] pipe writeCount. --- t1/src/T1.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 2320fa37c..1fa8c62c8 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -800,10 +800,10 @@ class T1(val parameter: T1Parameter) lane.loadDataInLSUWriteQueue := lsu.dataInWriteQueue(index) // 2 + 3 = 5 - val rowWith: Int = log2Ceil(parameter.datapathWidth / 8) + log2Ceil(parameter.laneNumber) - lane.writeCount := - (requestReg.bits.writeByte >> rowWith).asUInt + - (requestReg.bits.writeByte(rowWith - 1, 0) > ((parameter.datapathWidth / 8) * index).U) + val rowWith: Int = log2Ceil(parameter.datapathWidth / 8) + log2Ceil(parameter.laneNumber) + val writeCounter: UInt = (requestReg.bits.writeByte >> rowWith).asUInt + + (requestReg.bits.writeByte(rowWith - 1, 0) > ((parameter.datapathWidth / 8) * index).U) + lane.writeCount := Pipe(true.B, writeCounter, parameter.laneRequestShifterSize(index)).bits // token manager tokenManager.instructionFinish(index) := instructionFinishedPipe