From 93cc8056243bc4e0304eab1dee1ea51d43868080 Mon Sep 17 00:00:00 2001 From: Shupei Fan Date: Mon, 2 Dec 2024 07:29:34 +0000 Subject: [PATCH] [t1emu & t1rocketemu] rename ClockGen -> VerbatimModule --- difftest/dpi_t1emu/src/lib.rs | 2 +- difftest/dpi_t1rocketemu/src/lib.rs | 2 +- t1emu/src/TestBench.scala | 16 ++++++++-------- t1emu/vsrc/{ClockGen.sv => VerbatimModule.sv} | 5 ++++- t1rocketemu/src/TestBench.scala | 16 ++++++++-------- .../vsrc/{ClockGen.sv => VerbatimModule.sv} | 5 ++++- 6 files changed, 26 insertions(+), 20 deletions(-) rename t1emu/vsrc/{ClockGen.sv => VerbatimModule.sv} (92%) rename t1rocketemu/vsrc/{ClockGen.sv => VerbatimModule.sv} (95%) diff --git a/difftest/dpi_t1emu/src/lib.rs b/difftest/dpi_t1emu/src/lib.rs index b2b0344e6..f9186c193 100644 --- a/difftest/dpi_t1emu/src/lib.rs +++ b/difftest/dpi_t1emu/src/lib.rs @@ -44,7 +44,7 @@ impl OnlineArgs { } } -// keep in sync with TestBench.ClockGen +// keep in sync with TestBench.verbatimModule // the value is measured in simulation time unit pub const CYCLE_PERIOD: u64 = 20000; diff --git a/difftest/dpi_t1rocketemu/src/lib.rs b/difftest/dpi_t1rocketemu/src/lib.rs index e1016145c..f4ef0d48a 100644 --- a/difftest/dpi_t1rocketemu/src/lib.rs +++ b/difftest/dpi_t1rocketemu/src/lib.rs @@ -32,7 +32,7 @@ impl OnlineArgs { } } -// keep in sync with TestBench.ClockGen +// keep in sync with TestBench.verbatimModule // the value is measured in simulation time unit pub const CYCLE_PERIOD: u64 = 20000; diff --git a/t1emu/src/TestBench.scala b/t1emu/src/TestBench.scala index 5ad33558b..cfe02fdc3 100644 --- a/t1emu/src/TestBench.scala +++ b/t1emu/src/TestBench.scala @@ -39,23 +39,23 @@ class TestBench(val parameter: T1Parameter) val om: Property[ClassType] = IO(Output(Property[omType.Type]())) om := omInstance.getPropertyReference - val clockGen = Module(new ExtModule { + val verbatimModule = Module(new ExtModule { - override def desiredName = "ClockGen" + override def desiredName = "VerbatimModule" val clock = IO(Output(Bool())) val reset = IO(Output(Bool())) }) - def clock = clockGen.clock.asClock - def reset = clockGen.reset - override def implicitClock = clockGen.clock.asClock - override def implicitReset = clockGen.reset + def clock = verbatimModule.clock.asClock + def reset = verbatimModule.reset + override def implicitClock = verbatimModule.clock.asClock + override def implicitReset = verbatimModule.reset val dut: Instance[T1] = SerializableModuleGenerator(classOf[T1], parameter).instance() val simulationTime: UInt = RegInit(0.U(64.W)) simulationTime := simulationTime + 1.U - dut.io.clock := clockGen.clock.asClock - dut.io.reset := clockGen.reset + dut.io.clock := clock + dut.io.reset := reset omInstance.t1In := Property(dut.io.om.asAnyClassType) // uint32_t -> svBitVecVal -> reference type with 7 length. diff --git a/t1emu/vsrc/ClockGen.sv b/t1emu/vsrc/VerbatimModule.sv similarity index 92% rename from t1emu/vsrc/ClockGen.sv rename to t1emu/vsrc/VerbatimModule.sv index 3a5dae127..3d1dfb3f2 100644 --- a/t1emu/vsrc/ClockGen.sv +++ b/t1emu/vsrc/VerbatimModule.sv @@ -1,5 +1,8 @@ -module ClockGen(output reg clock, output reg reset); +module VerbatimModule(output reg clock, output reg reset); + // This module contains everything we can not represent in Chisel currently, + // including clock gen, plusarg parsing, sim control, etc + // // plusargs: "T" denotes being present only if trace is enabled // +t1_elf_file (required) path to elf file, parsed in DPI side // +t1_wave_path (required T) path to wave dump file diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index 2b59c97c6..a25ce485f 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -39,18 +39,18 @@ class TestBench(val parameter: T1RocketTileParameter) val om: Property[ClassType] = IO(Output(Property[omType.Type]())) om := omInstance.getPropertyReference - val clockGen = Module(new ExtModule { - override def desiredName = "ClockGen" + val verbatimModule = Module(new ExtModule { + override def desiredName = "VerbatimModule" val clock = IO(Output(Bool())) val reset = IO(Output(Bool())) val initFlag = IO(Output(Bool())) val idle = IO(Input(Bool())) }) - def clock = clockGen.clock.asClock - def reset = clockGen.reset - def initFlag = clockGen.initFlag - override def implicitClock = clockGen.clock.asClock - override def implicitReset = clockGen.reset + def clock = verbatimModule.clock.asClock + def reset = verbatimModule.reset + def initFlag = verbatimModule.initFlag + override def implicitClock = verbatimModule.clock.asClock + override def implicitReset = verbatimModule.reset val dut: Instance[T1RocketTile] = SerializableModuleGenerator(classOf[T1RocketTile], parameter).instance() omInstance.t1RocketTileIn := Property(dut.io.om.asAnyClassType) @@ -303,7 +303,7 @@ class TestBench(val parameter: T1RocketTileParameter) } // t1 quit - clockGen.idle := t1Probe.idle && rocketProbe.idle + verbatimModule.idle := t1Probe.idle && rocketProbe.idle // t1rocket ProfData layer.block(layers.Verification) { diff --git a/t1rocketemu/vsrc/ClockGen.sv b/t1rocketemu/vsrc/VerbatimModule.sv similarity index 95% rename from t1rocketemu/vsrc/ClockGen.sv rename to t1rocketemu/vsrc/VerbatimModule.sv index 4109efabd..6f4b2dd50 100644 --- a/t1rocketemu/vsrc/ClockGen.sv +++ b/t1rocketemu/vsrc/VerbatimModule.sv @@ -1,10 +1,13 @@ -module ClockGen( +module VerbatimModule( output reg clock, output reg reset, output reg initFlag, input wire idle ); + // This module contains everything we can not represent in Chisel currently, + // including clock gen, plusarg parsing, sim control, etc + // // plusargs: "T" denotes being present only if trace is enabled // +t1_elf_file (required) path to elf file, parsed in DPI side // +t1_wave_path (required T) path to wave dump file