From 7d5826a7eac320a29676db7b155f907dd9d15bc2 Mon Sep 17 00:00:00 2001
From: Shupei Fan <dymarkfan@outlook.com>
Date: Sun, 15 Sep 2024 17:16:15 +0000
Subject: [PATCH] [t1rocketemu] profile probe ...

---
 rocketv/src/RocketCore.scala    |  8 ++++++++
 t1rocket/src/T1RocketTile.scala |  9 +++++++++
 t1rocketemu/src/TestBench.scala | 13 +++++++++++--
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index 67e95ea1f..f54925a53 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -49,6 +49,9 @@ class RocketProbe(param: RocketParameter) extends Bundle {
   val idle:          Bool                       = Bool()
   // fpu score board
   val fpuScoreboard: Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe)
+
+  val wbRegPc:       UInt                       = UInt(param.iBufParameter.vaddrBitsExtended.W)
+  val t1IssueEnq:    Option[DecoupledIO[T1Issue]] = Option.when(param.usingT1)(DecoupledIO(new T1Issue(param.xLen, param.vLen)))
 }
 
 object RocketParameter {
@@ -1625,6 +1628,11 @@ class Rocket(val parameter: RocketParameter)
         }.getOrElse(false.B) || t1RetireQueue.map(q => q.io.deq.fire).getOrElse(false.B)
         probeWire.idle      := vectorEmpty
 
+        probeWire.wbRegPc := wbRegPc
+        probeWire.t1IssueEnq.foreach { case t1IssueEnq =>
+          t1IssueEnq := t1IssueQueue.io.enq
+        }
+
         probeWire.fpuScoreboard.foreach { case fpProbe =>
           fpProbe.memSetScoreBoard     := wbValid && wbDcacheMiss && wbRegDecodeOutput(parameter.decoderParameter.wfd)
           fpProbe.vectorSetScoreBoard  := wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && Option
diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala
index 8901f28d4..9391e8f2f 100644
--- a/t1rocket/src/T1RocketTile.scala
+++ b/t1rocket/src/T1RocketTile.scala
@@ -56,6 +56,9 @@ import org.chipsalliance.t1.rtl.{
   T1Probe,
   VFUInstantiateParameter
 }
+import chisel3.util.DecoupledIO
+import org.chipsalliance.t1.rtl.T1Issue
+import org.chipsalliance.rocketv.T1Retire
 
 object T1RocketTileParameter {
   implicit def bitSetP: upickle.default.ReadWriter[BitSet] = upickle.default
@@ -473,6 +476,9 @@ class T1RocketProbe(parameter: T1RocketTileParameter) extends Bundle {
   val rocketProbe: RocketProbe      = Output(new RocketProbe(parameter.rocketParameter))
   val fpuProbe:    Option[FPUProbe] = parameter.fpuParameter.map(param => Output(new FPUProbe(param)))
   val t1Probe:     T1Probe          = Output(new T1Probe(parameter.t1Parameter))
+
+  val t1IssueDeq:  DecoupledIO[T1Issue] = DecoupledIO(new T1Issue(parameter.xLen, parameter.vLen))
+  val t1Retire:    T1Retire         = Output(new T1Retire(parameter.xLen))
 }
 
 class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle {
@@ -616,5 +622,8 @@ class T1RocketTile(val parameter: T1RocketTileParameter)
     probeWire.fpuProbe.foreach { fpuProbe =>
       fpuProbe := probe.read(fpu.get.io.fpuProbe)
     }
+
+    probeWire.t1IssueDeq := t1.io.issue
+    probeWire.t1Retire := t1.io.retire
   }
 }
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
index 909accac9..c993f2704 100644
--- a/t1rocketemu/src/TestBench.scala
+++ b/t1rocketemu/src/TestBench.scala
@@ -331,13 +331,22 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
 
   // t1rocket ProfData
   layer.block(layers.Verification) {
+    val param = generator.parameter
     val profData = Module(new Module {
       override def desiredName: String = "ProfData"
-      val probe = IO(Input(new T1RocketProbe(generator.parameter)))
+      val probe = IO(Input(new T1RocketProbe(param)))
+
+      val t1IssueEnqPc = WireInit(probe.rocketProbe.wbRegPc)
+      val t1IssueEnq = WireInit(probe.rocketProbe.t1IssueEnq.get)
+      val t1IssueDeq = WireInit(probe.t1IssueDeq)
+      val t1Retire = WireInit(probe.t1Retire)
 
       dontTouch(this.clock)
       dontTouch(this.reset)
-      dontTouch(probe)
+      dontTouch(t1IssueEnq)
+      dontTouch(t1IssueEnq)
+      dontTouch(t1IssueDeq)
+      dontTouch(t1Retire)
     })
     profData.probe := t1RocketProbe
   }