From 7b8eb13a6500362876e3a9c00e646c073517150b Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Tue, 6 Aug 2024 13:52:58 +0800 Subject: [PATCH] [ipemu] refactor to an single Probe to avoid using Record --- ipemu/src/TestBench.scala | 24 ++++++++---------------- t1/src/Lane.scala | 23 ++++++++--------------- t1/src/T1.scala | 26 ++++++-------------------- t1/src/lsu/LSU.scala | 4 ++-- t1/src/vrf/VRF.scala | 4 ++-- 5 files changed, 26 insertions(+), 55 deletions(-) diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala index 21c3ad75a3..c3c96b318a 100644 --- a/ipemu/src/TestBench.scala +++ b/ipemu/src/TestBench.scala @@ -190,32 +190,24 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) // Events for difftest and performance modeling - val laneProbes = dut.io.laneProbes.zipWithIndex.map { - case (p, idx) => - val wire = Wire(p.cloneType).suggestName(s"lane${idx}Probe") - wire := probe.read(p) - wire + // Probes + val laneProbes = t1Probe.laneProbes.zipWithIndex.map { + case (lane, i) => lane.suggestName(s"lane${i}Probe") } - val lsuProbe = probe.read(dut.io.lsuProbe).suggestName("lsuProbe") + val lsuProbe = t1Probe.lsuProbe.suggestName("lsuProbe") val storeUnitProbe = lsuProbe.storeUnitProbe.suggestName("storeUnitProbe") val otherUnitProbe = lsuProbe.otherUnitProbe.suggestName("otherUnitProbe") - val laneVrfProbes = dut.io.laneVrfProbes.zipWithIndex.map { - case (p, idx) => - val wire = Wire(p.cloneType).suggestName(s"lane${idx}VrfProbe") - wire := probe.read(p) - wire - } - // vrf write - laneVrfProbes.zipWithIndex.foreach { + laneProbes.zipWithIndex.foreach { case (lane, i) => - when(lane.valid)( + val vrf = lane.vrfProbe.suggestName(s"lane${i}VrfProbe") + when(vrf.valid)( printf( - cf"""{"event":"VrfWrite","issue_idx":${lane.requestInstruction},"vd":${lane.requestVd},"offset":${lane.requestOffset},"mask":"${lane.requestMask}%x","data":"${lane.requestData}%x","lane":$i,"cycle":${simulationTime}}\n""" + cf"""{"event":"VrfWrite","issue_idx":${vrf.requestInstruction},"vd":${vrf.requestVd},"offset":${vrf.requestOffset},"mask":"${vrf.requestMask}%x","data":"${vrf.requestData}%x","lane":$i,"cycle":${simulationTime}}\n""" ) ) } diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index 49ddff3ee5..59a7eb8a66 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -55,18 +55,15 @@ class LaneWriteProbe(instructionIndexBits: Int) extends Bundle { class LaneProbe(parameter: LaneParameter) extends Bundle { val slots = Vec(parameter.chainingSize, new LaneSlotProbe(parameter.instructionIndexBits)) - // @todo @Clo91eaf remove valid here, add stall := valid & !ready - val laneRequestValid: Bool = Bool() - // @todo remove it. - val laneRequestReady: Bool = Bool() + val laneRequestStall: Bool = Bool() // @todo @Clo91eaf change to occupied for each slot. val lastSlotOccupied: Bool = Bool() - // @todo replace it with VRFProbe - val vrfInstructionWriteReportReady: Bool = Bool() val instructionFinished: UInt = UInt(parameter.chainingSize.W) val instructionValid: UInt = UInt(parameter.chainingSize.W) val crossWriteProbe: Vec[ValidIO[LaneWriteProbe]] = Vec(2, Valid(new LaneWriteProbe(parameter.instructionIndexBits))) + + val vrfProbe: VRFProbe = new VRFProbe(parameter.vrfParam) } object LaneParameter { @@ -314,11 +311,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val vrfReadyToStore: Bool = IO(Output(Bool())) @public - val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter)))) - val probeWire: LaneProbe = Wire(new LaneProbe(parameter)) - define(probe, ProbeValue(probeWire)) - @public - val vrfProbe = IO(Output(Probe(new VRFProbe(parameter.vrfParam)))) + val laneProbe = IO(Output(Probe(new LaneProbe(parameter)))) + val probeWire = Wire(new LaneProbe(parameter)) + define(laneProbe, ProbeValue(probeWire)) @public val vrfAllocateIssue: Bool = IO(Output(Bool())) @@ -328,7 +323,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ /** VRF instantces. */ val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam)) - define(vrfProbe, vrf.probe) /** TODO: review later */ @@ -1217,10 +1211,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ tokenManager.topWriteDeq.bits := allVrfWriteAfterCheck(parameter.chainingSize).instructionIndex // probe wire - probeWire.laneRequestValid := laneRequest.valid - probeWire.laneRequestReady := laneRequest.ready + probeWire.laneRequestStall := laneRequest.valid && !laneRequest.ready probeWire.lastSlotOccupied := slotOccupied.last - probeWire.vrfInstructionWriteReportReady := vrf.instructionWriteReport.ready probeWire.instructionFinished := instructionFinished probeWire.instructionValid := instructionValid probeWire.crossWriteProbe.zip(writeBusPort).foreach {case (pb, port) => @@ -1228,4 +1220,5 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ pb.bits.writeTag := port.deq.bits.instructionIndex pb.bits.writeMask := port.deq.bits.mask } + probeWire.vrfProbe := probe.read(vrf.vrfProbe) } diff --git a/t1/src/T1.scala b/t1/src/T1.scala index af110821c1..5a36bb040b 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -304,6 +304,9 @@ class T1Probe(parameter: T1Parameter) extends Bundle { val instructionValid: UInt = UInt((parameter.chainingSize * 2).W) // instruction index for check rd val responseCounter: UInt = UInt(parameter.instructionIndexBits.W) + // probes + val lsuProbe: LSUProbe = new LSUProbe(parameter.lsuParameters) + val laneProbes: Vec[LaneProbe] = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam)) } class T1Interface(parameter: T1Parameter) extends Record { @@ -314,11 +317,7 @@ class T1Interface(parameter: T1Parameter) extends Record { def highBandwidthLoadStorePort: AXI4RWIrrevocable = elements("highBandwidthLoadStorePort").asInstanceOf[AXI4RWIrrevocable] def indexedLoadStorePort: AXI4RWIrrevocable = elements("indexedLoadStorePort").asInstanceOf[AXI4RWIrrevocable] def om: Property[ClassType] = elements("om").asInstanceOf[Property[ClassType]] - // TODO: refactor to an single Probe to avoid using Record on the [[T1Interface]]. - def lsuProbe: LSUProbe = elements("lsuProbe").asInstanceOf[LSUProbe] def t1Probe: T1Probe = elements("t1Probe").asInstanceOf[T1Probe] - def laneProbes: Seq[LaneProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}Probe").asInstanceOf[LaneProbe]) - def laneVrfProbes: Seq[VRFProbe] = Seq.tabulate(parameter.laneNumber)(i => elements(s"lane${i}VrfProbe").asInstanceOf[VRFProbe]) val elements: SeqMap[String, Data] = SeqMap.from( Seq( "clock" -> Input(Clock()), @@ -328,15 +327,8 @@ class T1Interface(parameter: T1Parameter) extends Record { "highBandwidthLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter), "indexedLoadStorePort" -> new AXI4RWIrrevocable(parameter.axi4BundleParameter.copy(dataWidth=32)), "om" -> Output(Property[AnyClassType]()), - "lsuProbe" -> Output(Probe(new LSUProbe(parameter.lsuParameters))), "t1Probe" -> Output(Probe(new T1Probe(parameter))), - ) ++ - Seq.tabulate(parameter.laneNumber)( - i => s"lane${i}Probe" -> Output(Probe(new LaneProbe(parameter.laneParam))) - ) ++ - Seq.tabulate(parameter.laneNumber)( - i => s"lane${i}VrfProbe" -> Output(Probe(new VRFProbe(parameter.laneParam.vrfParam))) - ) + ) ) } @@ -1583,15 +1575,7 @@ class T1(val parameter: T1Parameter) lane } - laneVec.zipWithIndex.foreach { case (lane, index) => - define(io.laneProbes(index), lane.probe) - define(io.laneVrfProbes(index), lane.vrfProbe) - } - omInstance.lanesIn := Property(laneVec.map(_.om.asAnyClassType)) - - define(io.lsuProbe, lsu._probe) - dataInWritePipeVec := VecInit(laneVec.map(_.writeQueueValid)) // 连lsu @@ -1745,6 +1729,8 @@ class T1(val parameter: T1Parameter) !slots.last.state.sMaskUnitExecution && !slots.last.state.idle, indexToOH(slots.last.record.instructionIndex, parameter.chainingSize * 2)).asUInt probeWire.responseCounter := responseCounter + probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) } + probeWire.lsuProbe := probe.read(lsu.lsuProbe) // new V Request from core diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index a938973dcb..9cb3b7d58c 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -246,9 +246,9 @@ class LSU(param: LSUParameter) extends Module { ) @public - val _probe = IO(Output(Probe(new LSUProbe(param)))) + val lsuProbe = IO(Output(Probe(new LSUProbe(param)))) val probeWire = Wire(new LSUProbe(param)) - define(_probe, ProbeValue(probeWire)) + define(lsuProbe, ProbeValue(probeWire)) // read vrf val otherTryReadVrf: UInt = Mux(otherUnit.vrfReadDataPorts.valid, otherUnit.status.targetLane, 0.U) diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index 61df7864bd..724ef63723 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -564,9 +564,9 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar * Probe */ @public - val probe = IO(Output(Probe(new VRFProbe(parameter)))) + val vrfProbe = IO(Output(Probe(new VRFProbe(parameter)))) val probeWire = Wire(new VRFProbe(parameter)) - define(probe, ProbeValue(probeWire)) + define(vrfProbe, ProbeValue(probeWire)) probeWire.valid := writePipe.valid probeWire.requestVd := writePipe.bits.vd