From 763c7bdaf1d34746c97c7f116d3b1b67c0463c89 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Fri, 26 Jul 2024 15:50:00 +0800
Subject: [PATCH] [rocketv] connect csr for vector.

---
 rocketv/src/Bundle.scala     |  8 ++++++++
 rocketv/src/CSR.scala        | 11 +++++++++++
 rocketv/src/RocketCore.scala |  4 ++++
 3 files changed, 23 insertions(+)

diff --git a/rocketv/src/Bundle.scala b/rocketv/src/Bundle.scala
index f7b8161c26..2c4dc25ca1 100644
--- a/rocketv/src/Bundle.scala
+++ b/rocketv/src/Bundle.scala
@@ -492,6 +492,14 @@ class DCSR extends Bundle {
   val prv = UInt(PRV.SZ.W)
 }
 
+class VCSR extends Bundle {
+  val vtype: UInt = UInt(32.W)
+  val vl:    UInt = UInt(32.W)
+  val vcsr: UInt = UInt(32.W)
+  val vstart: UInt = UInt(32.W)
+}
+
+
 class MIP(nLocalInterrupts: Int) extends Bundle {
   val lip = Vec(nLocalInterrupts, Bool())
   val zero1 = Bool()
diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala
index 266a339a52..aa72c4fdaa 100644
--- a/rocketv/src/CSR.scala
+++ b/rocketv/src/CSR.scala
@@ -279,6 +279,7 @@ class CSRInterface(parameter: CSRParameter) extends Bundle {
   val fiom = Output(Bool())
   val vectorCsr = Option.when(parameter.usingVector)(Input(Bool()))
   val wbRegRS2 = Option.when(parameter.usingVector)(Input(UInt(parameter.xLen.W)))
+  val csrToVector = Option.when(parameter.usingVector)(Output(new VCSR))
   // @todo custom CSR
   val customCSRs = Vec(parameter.customCSRSize, new CustomCSRIO(parameter.xLen))
 }
@@ -1678,6 +1679,16 @@ class CSR(val parameter: CSRParameter)
 
   // update csr for vector
   if (usingVector) {
+    // connect csr for vector
+    val vtype = vector.get.states("vill") ## 0.U(23.W) ## vector.get.states("vma") ##
+      vector.get.states("vta") ## vector.get.states("vsew") ## vector.get.states("vlmul")
+    val vcsr = vector.get.states("vxrm") ## vector.get.states("vxsat")
+    io.csrToVector.foreach {v =>
+      v.vtype := vtype
+      v.vl := vector.get.states("vl")
+      v.vcsr := vcsr
+      v.vstart := vector.get.states("vstart")
+    }
     // set vl type
     val vsetvli = !io.inst(0)(31)
     val vsetivli = io.inst(0)(31, 30).andR
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index 7470b4c3ec..5a745e80aa 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -1353,6 +1353,10 @@ class Rocket(val parameter: RocketParameter)
       t1IssueQueue.io.enq.bits.instruction := wbRegInstruction
       t1IssueQueue.io.enq.bits.rs1Data := wbRegWdata
       t1IssueQueue.io.enq.bits.rs2Data := wbRegRS2
+      t1IssueQueue.io.enq.bits.vtype := csr.io.csrToVector.get.vtype
+      t1IssueQueue.io.enq.bits.vl := csr.io.csrToVector.get.vl
+      t1IssueQueue.io.enq.bits.vstart := csr.io.csrToVector.get.vstart
+      t1IssueQueue.io.enq.bits.vcsr := csr.io.csrToVector.get.vcsr
       t1.issue.valid := t1IssueQueue.io.deq.valid
       t1.issue.bits := t1IssueQueue.io.deq.bits
       t1IssueQueue.io.deq.ready := t1.issue.ready