From 732d5363de9f6848ce4ff81f5dd8ea27435cbb50 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Fri, 22 Sep 2023 19:49:20 +0800 Subject: [PATCH] [emulator] add probe unit Signed-off-by: Avimitin --- elaborator/src/PerfMonitor.scala | 14 ++++++++++++++ v/src/lsu/LoadUnit.scala | 9 +++++++++ 2 files changed, 23 insertions(+) create mode 100644 elaborator/src/PerfMonitor.scala diff --git a/elaborator/src/PerfMonitor.scala b/elaborator/src/PerfMonitor.scala new file mode 100644 index 0000000000..a870edaeec --- /dev/null +++ b/elaborator/src/PerfMonitor.scala @@ -0,0 +1,14 @@ +package elaborate.dpi + +import chisel3._ + +class LoadUnitMonitor extends DPIModule { + override val isImport = true; + + val clock = dpiTrigger("clock", Input(Bool())) + + val statusIdle = dpiIn("LoadUnitStatusIdle", Input(Bool())) + val writeReadyForLSU = dpiIn("LoadUnitWriteReadyForLSU", Input(Bool())) + + override val trigger: String = s"always @(posedge ${clock.name})"; +} diff --git a/v/src/lsu/LoadUnit.scala b/v/src/lsu/LoadUnit.scala index f58dd2e464..2689452406 100644 --- a/v/src/lsu/LoadUnit.scala +++ b/v/src/lsu/LoadUnit.scala @@ -6,6 +6,7 @@ import chisel3._ import chisel3.util._ import lsu.LSUBaseStatus import tilelink.{TLChannelA, TLChannelD} +import chisel3.probe.{Probe, ProbeValue, define} class cacheLineDequeueBundle(param: MSHRParam) extends Bundle { val data: UInt = UInt((param.cacheLineSize * 8).W) @@ -245,4 +246,12 @@ class LoadUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic { status.endAddress := ((lsuRequestReg.rs1Data >> param.cacheLineBits).asUInt + cacheLineNumberReg) ## 0.U(param.cacheLineBits.W) dontTouch(status) + + /** + * Probes for fetching internal signals + */ + val probeStatus: LSUBaseStatus = IO(Output(Probe(chiselTypeOf(status)))) + define(probeStatus, ProbeValue(status)) + val probeWriteReadyForLSU: Bool = IO(Output(Probe(chiselTypeOf(writeReadyForLsu)))) + define(probeWriteReadyForLSU, ProbeValue(writeReadyForLsu)) }