diff --git a/t1-ddr.ld b/t1-ddr.ld
new file mode 100644
index 0000000000..19e347720c
--- /dev/null
+++ b/t1-ddr.ld
@@ -0,0 +1,35 @@
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+MEMORY {
+  SCALAR (RWX) : ORIGIN = 0x20000000, LENGTH = 512M /* put first to set it as default */
+  MMIO   (RW)  : ORIGIN = 0x00000000, LENGTH = 512M
+  DDR    (RW)  : ORIGIN = 0x40000000, LENGTH = 2048M
+  SRAM   (RW)  : ORIGIN = 0xc0000000, LENGTH = 4M /* TODO: read from config */
+}
+
+SECTIONS {
+  . = ORIGIN(SCALAR);
+  .text           : { *(.text .text.*) }
+  . = ALIGN(0x1000);
+
+  .data           : { *(.data .data.*) }
+  . = ALIGN(0x1000);
+
+  .sdata          : { *(.sdata .sdata.*) }
+  . = ALIGN(0x1000);
+
+  .srodata          : { *(.srodata .srodata.*) }
+  . = ALIGN(0x1000);
+
+  .bss            : { *(.bss .bss.*) }
+  _end = .; PROVIDE (end = .);
+
+  . = ORIGIN(SRAM);
+  .vdata : { *(.vdata .vdata.*) } >DDR
+
+  .vbss (TYPE = SHT_NOBITS) : { *(.vbss .vbss.*) } >DDR
+
+  __stacktop = ORIGIN(SCALAR) + LENGTH(SCALAR);  /* put stack on the top of SCALAR */
+  __heapbegin = ORIGIN(DDR);  /* put heap on the begin of DDR */
+}
diff --git a/tests/codegen/default.nix b/tests/codegen/default.nix
index 4bf91db831..7707e2a239 100644
--- a/tests/codegen/default.nix
+++ b/tests/codegen/default.nix
@@ -29,6 +29,8 @@ let
           ${riscv-vector-test}/bin/single \
             -VLEN "${builtins.toString rtlDesignMetadata.vlen}" \
             -XLEN "${builtins.toString rtlDesignMetadata.xlen}" \
+            # Golang only accept "-flag=value" pattern to set value for flag, don't mess around with other cmd line option.
+            -float16=false \
             -repeat 16 \
             -testfloat3level 2 \
             -configfile ${riscv-vector-test}/configs/${rawCaseName}.toml \