From 492d6589c1c6b788d0cea79fd973076d3459a2b6 Mon Sep 17 00:00:00 2001
From: unlsycn <unlsycn@unlsycn.com>
Date: Mon, 2 Dec 2024 05:58:36 +0000
Subject: [PATCH] fix sram module name

---
 rocketv/src/SRAM.scala | 2 +-
 t1/src/SRAM.scala      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/rocketv/src/SRAM.scala b/rocketv/src/SRAM.scala
index 29836be71..7d55a79f2 100644
--- a/rocketv/src/SRAM.scala
+++ b/rocketv/src/SRAM.scala
@@ -339,7 +339,7 @@ object SRAM {
     val mem = Instantiate(
       new SRAMBlackbox(
         new CIRCTSRAMParameter(
-          s"sram_${size}x${tpe.getWidth}",
+          s"sram_${numReadPorts}R_${numWritePorts}W_${numReadwritePorts}RW_${size}x${tpe.getWidth}",
           numReadPorts,
           numWritePorts,
           numReadwritePorts,
diff --git a/t1/src/SRAM.scala b/t1/src/SRAM.scala
index 29836be71..7d55a79f2 100644
--- a/t1/src/SRAM.scala
+++ b/t1/src/SRAM.scala
@@ -339,7 +339,7 @@ object SRAM {
     val mem = Instantiate(
       new SRAMBlackbox(
         new CIRCTSRAMParameter(
-          s"sram_${size}x${tpe.getWidth}",
+          s"sram_${numReadPorts}R_${numWritePorts}W_${numReadwritePorts}RW_${size}x${tpe.getWidth}",
           numReadPorts,
           numWritePorts,
           numReadwritePorts,