From 47e1b3a30b9052af33b26241e66f3aa3c44f2aae Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 24 Jan 2024 04:40:24 +0800 Subject: [PATCH] [subsystem] fix RTL for upstream circt --- nix/t1/_sources/generated.json | 8 +++---- nix/t1/_sources/generated.nix | 8 +++---- rocket/src/AbstractT1.scala | 1 + rocket/src/CSR.scala | 9 ++++---- rocket/src/DCache.scala | 6 ++--- rocket/src/Frontend.scala | 6 ++--- rocket/src/HellaCache.scala | 8 +++---- rocket/src/ICache.scala | 5 ++-- rocket/src/RocketCore.scala | 34 +++++++++++++++++----------- rocket/src/RocketTile.scala | 20 ++++++++-------- rocket/src/ScratchpadSlavePort.scala | 6 ++--- subsystem/src/LazyT1.scala | 10 ++++---- subsystem/src/Subsystem.scala | 27 ++++++++++++++-------- subsystememu/src/Testbench.scala | 5 ++-- t1/src/VectorFunctionUnit.scala | 4 ++-- 15 files changed, 86 insertions(+), 71 deletions(-) diff --git a/nix/t1/_sources/generated.json b/nix/t1/_sources/generated.json index 24e2b5158f..7f5aaa5803 100644 --- a/nix/t1/_sources/generated.json +++ b/nix/t1/_sources/generated.json @@ -101,7 +101,7 @@ }, "rocket-chip": { "cargoLocks": null, - "date": "2023-11-25", + "date": "2024-01-28", "extract": null, "name": "rocket-chip", "passthru": null, @@ -113,11 +113,11 @@ "name": null, "owner": "chipsalliance", "repo": "rocket-chip", - "rev": "b3fa8df9bfb3a6d5b1d57dc4a0633fc6028242ac", - "sha256": "sha256-hQcjdwIObdMLrmLaK/yGTdClbbGlVC61K/o6dehiHFU=", + "rev": "baa9f4523f846831f03761179c209fb633c68f8d", + "sha256": "sha256-kBfeLpliTc2cj3ZUNe1CUKj1qhpJBWglgcuXtuQVZco=", "type": "github" }, - "version": "b3fa8df9bfb3a6d5b1d57dc4a0633fc6028242ac" + "version": "baa9f4523f846831f03761179c209fb633c68f8d" }, "rocket-chip-inclusive-cache": { "cargoLocks": null, diff --git a/nix/t1/_sources/generated.nix b/nix/t1/_sources/generated.nix index 63aded7d8d..238cdfb988 100644 --- a/nix/t1/_sources/generated.nix +++ b/nix/t1/_sources/generated.nix @@ -63,15 +63,15 @@ }; rocket-chip = { pname = "rocket-chip"; - version = "b3fa8df9bfb3a6d5b1d57dc4a0633fc6028242ac"; + version = "baa9f4523f846831f03761179c209fb633c68f8d"; src = fetchFromGitHub { owner = "chipsalliance"; repo = "rocket-chip"; - rev = "b3fa8df9bfb3a6d5b1d57dc4a0633fc6028242ac"; + rev = "baa9f4523f846831f03761179c209fb633c68f8d"; fetchSubmodules = false; - sha256 = "sha256-hQcjdwIObdMLrmLaK/yGTdClbbGlVC61K/o6dehiHFU="; + sha256 = "sha256-kBfeLpliTc2cj3ZUNe1CUKj1qhpJBWglgcuXtuQVZco="; }; - date = "2023-11-25"; + date = "2024-01-28"; }; rocket-chip-inclusive-cache = { pname = "rocket-chip-inclusive-cache"; diff --git a/rocket/src/AbstractT1.scala b/rocket/src/AbstractT1.scala index aefad6cc1f..a049ebab30 100644 --- a/rocket/src/AbstractT1.scala +++ b/rocket/src/AbstractT1.scala @@ -177,6 +177,7 @@ trait HasLazyT1Module { this: RocketTileModuleImp => // TODO: make it configurable val maxCount: Int = 32 val vlMax: Int = 1024 + val xLen: Int = 32 val instructionQueue: Option[Queue[VectorRequest]] = core.t1Request.map(req => Module(new Queue(chiselTypeOf(req.bits), maxCount))) diff --git a/rocket/src/CSR.scala b/rocket/src/CSR.scala index 7cd6c43db7..4492abdfe4 100644 --- a/rocket/src/CSR.scala +++ b/rocket/src/CSR.scala @@ -231,9 +231,9 @@ class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val virtualSystemIllegal = Output(Bool()) } -class CSRFileIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { +class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungatedClock = Input(Clock()) - val interrupts = Input(new CoreInterrupts()) + val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) @@ -287,14 +287,15 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle with HasCoreParameter */ class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), - customCSRs: Seq[CustomCSR] = Nil + customCSRs: Seq[CustomCSR] = Nil, + hasBeu: Boolean )( implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val vector = Option.when(usingVector)(new csr.V(vLen, usingHypervisor)) - val io = IO(new CSRFileIO { + val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) }) diff --git a/rocket/src/DCache.scala b/rocket/src/DCache.scala index e916686879..bf54c223c0 100644 --- a/rocket/src/DCache.scala +++ b/rocket/src/DCache.scala @@ -82,8 +82,8 @@ class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } -class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) - extends HellaCache(staticIdForMetadataUseOnly)(p) { +class DCache(val crossing: ClockCrossingType)(implicit p: Parameters) + extends HellaCache()(p) { override lazy val module = new DCacheModule(this) } @@ -640,7 +640,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val atomics = if (edge.manager.anySupportLogical) { MuxLookup( s2_req.cmd, - WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))), + WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))( Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR)._2, diff --git a/rocket/src/Frontend.scala b/rocket/src/Frontend.scala index 705925f102..5ffe0fccbb 100644 --- a/rocket/src/Frontend.scala +++ b/rocket/src/Frontend.scala @@ -63,10 +63,10 @@ class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) { val progress = Output(Bool()) } -class Frontend(val icacheParams: ICacheParams, staticIdForMetadataUseOnly: Int)(implicit p: Parameters) +class Frontend(val icacheParams: ICacheParams)(implicit p: Parameters) extends LazyModule { lazy val module = new FrontendModule(this) - val icache = LazyModule(new ICache(icacheParams, staticIdForMetadataUseOnly)) + val icache = LazyModule(new ICache(icacheParams)) val masterNode = icache.masterNode val slaveNode = icache.slaveNode val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W))) @@ -418,7 +418,7 @@ class FrontendModule(outer: Frontend) /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */ trait HasICacheFrontend extends CanHavePTW { this: BaseTile => val module: HasICacheFrontendModule - val frontend = LazyModule(new Frontend(tileParams.icache.get, staticIdForMetadataUseOnly)) + val frontend = LazyModule(new Frontend(tileParams.icache.get)) tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits / 8) := frontend.masterNode connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes) frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode } diff --git a/rocket/src/HellaCache.scala b/rocket/src/HellaCache.scala index 03d7795a2b..1201972eb1 100644 --- a/rocket/src/HellaCache.scala +++ b/rocket/src/HellaCache.scala @@ -145,7 +145,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { /** Base classes for Diplomatic TL2 HellaCaches */ -abstract class HellaCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) +abstract class HellaCache()(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get @@ -155,7 +155,7 @@ abstract class HellaCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameter .getOrElse( Seq( TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache", + name = s"Core DCache", sourceId = IdRange(0, 1.max(cfg.nMSHRs)), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes) ) @@ -164,7 +164,7 @@ abstract class HellaCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameter protected def mmioClientParameters = Seq( TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache MMIO", + name = s"Core DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true ) @@ -234,7 +234,7 @@ case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache]( object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { assert(tile.tileParams.dcache.get.nMSHRs == 0) - new DCache(tile.staticIdForMetadataUseOnly, tile.crossing)(p) + new DCache(tile.crossing)(p) } } diff --git a/rocket/src/ICache.scala b/rocket/src/ICache.scala index 0a6a9eb1bb..08b5812ffe 100644 --- a/rocket/src/ICache.scala +++ b/rocket/src/ICache.scala @@ -77,9 +77,8 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICa * There will always be one way(the last way) used for I$, which cannot be allocated to ITIM. * * @param icacheParams parameter to this I$. - * @param staticIdForMetadataUseOnly metadata used for hart id. */ -class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int)(implicit p: Parameters) +class ICache(val icacheParams: ICacheParams)(implicit p: Parameters) extends LazyModule { lazy val module = new ICacheModule(this) @@ -111,7 +110,7 @@ class ICache(val icacheParams: ICacheParams, val staticIdForMetadataUseOnly: Int clients = Seq( TLMasterParameters.v1( sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint - name = s"Core ${staticIdForMetadataUseOnly} ICache" + name = s"ICache" ) ), requestFields = useVM.option(Seq()).getOrElse(Seq(AMBAProtField())) diff --git a/rocket/src/RocketCore.scala b/rocket/src/RocketCore.scala index c06371083c..51c3636cf6 100644 --- a/rocket/src/RocketCore.scala +++ b/rocket/src/RocketCore.scala @@ -6,6 +6,7 @@ package org.chipsalliance.t1.rocketcore import chisel3._ import chisel3.util._ import chisel3.util.experimental.decode.DecodeBundle +import freechips.rocketchip.tile.TileInterrupts import freechips.rocketchip.util._ import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.t1.rockettile.{VectorRequest, VectorResponse} @@ -14,7 +15,7 @@ import scala.collection.mutable.ArrayBuffer // TODO: remove it. import freechips.rocketchip.rocket.{Causes, MulDivParams, RocketCoreParams} -import freechips.rocketchip.tile.{CoreInterrupts, FPUCoreIO, HasCoreParameters} +import freechips.rocketchip.tile.{FPUCoreIO, HasCoreParameters} trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] @@ -30,8 +31,13 @@ trait HasRocketCoreParameters extends HasCoreParameters { require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") require(!usingConditionalZero, "Zicond is not yet implemented in ABLU") } +class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { + val buserror = Option.when(hasBeu)(Bool()) +} -class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with HasRocketCoreParameters { +class Rocket(flushOnFenceI: Boolean, hasBeu: Boolean)(implicit val p: Parameters) + extends Module + with HasRocketCoreParameters { // Checker require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") @@ -105,14 +111,14 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H case _ => true }.toSeq.distinct, pipelinedMul, - tile.dcache.flushOnFenceI + flushOnFenceI ) ) val lgNXRegs: Int = if (coreParams.useRVE) 4 else 5 val regAddrMask: Int = (1 << lgNXRegs) - 1 val hartid = IO(Input(UInt(hartIdLen.W))) - val interrupts = IO(Input(new CoreInterrupts())) + val interrupts = IO(Input(new CoreInterrupts(hasBeu))) val imem = IO(new FrontendIO) val dmem = IO(new HellaCacheIO) val ptw = IO(Flipped(new DatapathPTWIO())) @@ -214,7 +220,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H // instantiate modules // TODO: remove implicit parameter for them. - val csr: CSRFile = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls)) + val csr: CSRFile = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, hasBeu)) // TODO: move to Parameter Level or LazyModule level. /** Decoder instantiated, input from IF, output to ID. */ @@ -522,7 +528,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H exRegDecodeOutput(decoder.memCommand) := M_HFENCEV } - if (tile.dcache.flushOnFenceI) { + if (flushOnFenceI) { when(idDecodeOutput(decoder.fenceI)) { exRegMemSize := 0.U } @@ -770,9 +776,11 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H val wbSetSboard: Bool = wbDcacheMiss || Option.when(usingMulDiv)(wbRegDecodeOutput(decoder.div)).getOrElse(false.B) || - Option.when(usingVector){ - wbRegDecodeOutput(decoder.wxd) && wbRegDecodeOutput(decoder.vector) && !wbRegDecodeOutput(decoder.vectorCSR) - }.getOrElse(false.B) + Option + .when(usingVector) { + wbRegDecodeOutput(decoder.wxd) && wbRegDecodeOutput(decoder.vector) && !wbRegDecodeOutput(decoder.vectorCSR) + } + .getOrElse(false.B) val replayWbCommon: Bool = dmem.s2_nack || wbRegReplay val replayWbCsr: Bool = wbRegValid && csr.io.rwStall val replayWb: Bool = replayWbCommon || replayWbCsr @@ -980,7 +988,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H } // vector stall - val vectorLSUEmpty: Option[Bool] = Option.when(usingVector)(Wire(Bool())) + val vectorLSUEmpty: Option[Bool] = Option.when(usingVector)(Wire(Bool())) val vectorQueueFull: Option[Bool] = Option.when(usingVector)(Wire(Bool())) val vectorStall: Option[Bool] = Option.when(usingVector) { val vectorLSUNotClear = @@ -988,7 +996,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H (memRegValid && memRegDecodeOutput(decoder.vectorLSU)) || (wbRegValid && wbRegDecodeOutput(decoder.vectorLSU)) || !vectorLSUEmpty.get (idDecodeOutput(decoder.vector) && vectorQueueFull.get) || - (idDecodeOutput(decoder.mem) && !idDecodeOutput(decoder.vector) && vectorLSUNotClear) + (idDecodeOutput(decoder.mem) && !idDecodeOutput(decoder.vector) && vectorLSUNotClear) } val ctrlStalld: Bool = @@ -1096,7 +1104,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H val maxCount: Int = 32 val countWidth = log2Up(maxCount) - def counterManagement(size: Int, margin: Int = 0)(grant: Bool, release: Bool, flush: Option[Bool]=None) = { + def counterManagement(size: Int, margin: Int = 0)(grant: Bool, release: Bool, flush: Option[Bool] = None) = { val counter: UInt = RegInit(0.U(size.W)) val nextCount = counter + Mux(grant, 1.U(size.W), (-1.S(size.W)).asUInt) val updateCounter = grant ^ release @@ -1110,7 +1118,7 @@ class Rocket(tile: RocketTile)(implicit val p: Parameters) extends Module with H (empty, full) } // Maintain lsu counter - val lsuGrant: Bool = t1.valid && wbRegDecodeOutput(decoder.vectorLSU) + val lsuGrant: Bool = t1.valid && wbRegDecodeOutput(decoder.vectorLSU) val lsuRelease: Bool = response.fire && response.bits.mem val (lsuEmpty, _) = counterManagement(countWidth)(lsuGrant, lsuRelease) // Maintain vector counter diff --git a/rocket/src/RocketTile.scala b/rocket/src/RocketTile.scala index 3e8e503259..bc60d5c40a 100644 --- a/rocket/src/RocketTile.scala +++ b/rocket/src/RocketTile.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci.ClockSinkParameters -import freechips.rocketchip.subsystem.{CanAttachTile, RocketCrossingParams, TileCrossingParamsLike} +import freechips.rocketchip.subsystem.{CanAttachTile, RocketCrossingParams, HierarchicalElementCrossingParamsLike} import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ @@ -31,7 +31,7 @@ case class RocketTileParams( btb: Option[BTBParams] = Some(BTBParams()), dataScratchpadBytes: Int = 0, name: Option[String] = Some("tile"), - hartId: Int = 0, + tileId: Int = 0, beuAddr: Option[BigInt] = None, blockerCtrlAddr: Option[BigInt] = None, clockSinkParams: ClockSinkParameters = ClockSinkParameters(), @@ -39,7 +39,9 @@ case class RocketTileParams( extends InstantiableTileParams[RocketTile] { require(icache.isDefined) require(dcache.isDefined) - def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { + val baseName = "rockettile" + val uniqueName = s"${baseName}_$tileId" + def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): RocketTile = { new RocketTile(this, crossing, lookup) } } @@ -58,14 +60,14 @@ class RocketTile private ( // Private constructor ensures altered LazyModule.p is used implicitly def this( params: RocketTileParams, - crossing: TileCrossingParamsLike, + crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl )( implicit p: Parameters ) = this(params, crossing.crossingType, lookup, p) - val intOutwardNode = IntIdentityNode() + val intOutwardNode = rocketParams.beuAddr map { _ => IntIdentityNode() } val slaveNode = TLIdentityNode() val masterNode = visibilityNode @@ -84,7 +86,7 @@ class RocketTile private ( val bus_error_unit = rocketParams.beuAddr.map { a => val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a))) - intOutwardNode := beu.intNode + intOutwardNode.get := beu.intNode connectTLSlave(beu.node, xBytes) beu } @@ -121,7 +123,7 @@ class RocketTile private ( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } override lazy val module = new RocketTileModuleImp(this) @@ -150,7 +152,7 @@ class RocketTileModuleImp(outer: RocketTile) with HasICacheFrontendModule { Annotated.params(this, outer.rocketParams) - lazy val core = Module(new Rocket(outer)(outer.p)) + lazy val core = Module(new Rocket(outer.dcache.flushOnFenceI, outer.bus_error_unit.isDefined)(outer.p)) // Report unrecoverable error conditions; for now the only cause is cache ECC errors outer.reportHalt(List(outer.dcache.module.io.errors)) @@ -175,7 +177,7 @@ class RocketTileModuleImp(outer: RocketTile) beu.module.io.errors.icache := outer.frontend.module.io.errors } - core.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.bundle } + core.interrupts.nmi.foreach { nmi => nmi := outer.nmiSinkNode.get.bundle } // Pass through various external constants and reports that were bundle-bridged into the tile core.traceStall := outer.traceAuxSinkNode.bundle.stall diff --git a/rocket/src/ScratchpadSlavePort.scala b/rocket/src/ScratchpadSlavePort.scala index 517e783c77..17d4fb384f 100644 --- a/rocket/src/ScratchpadSlavePort.scala +++ b/rocket/src/ScratchpadSlavePort.scala @@ -71,13 +71,13 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto val req = Wire(new HellaCacheReq) req.cmd := MuxLookup( a.opcode, - M_XRD, + M_XRD)( Array( TLMessages.PutFullData -> M_XWR, TLMessages.PutPartialData -> M_PWR, TLMessages.ArithmeticData -> MuxLookup( a.param, - M_XRD, + M_XRD)( Array( TLAtomics.MIN -> M_XA_MIN, TLAtomics.MAX -> M_XA_MAX, @@ -88,7 +88,7 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto ), TLMessages.LogicalData -> MuxLookup( a.param, - M_XRD, + M_XRD)( Array( TLAtomics.XOR -> M_XA_XOR, TLAtomics.OR -> M_XA_OR, diff --git a/subsystem/src/LazyT1.scala b/subsystem/src/LazyT1.scala index 2464c6ad7d..27d6a412a2 100644 --- a/subsystem/src/LazyT1.scala +++ b/subsystem/src/LazyT1.scala @@ -6,16 +6,14 @@ package org.chipsalliance.t1.subsystem import chisel3._ import chisel3.experimental.SerializableModuleGenerator import freechips.rocketchip.diplomacy.AddressSet -import freechips.rocketchip.subsystem.{BaseSubsystem, HasTiles} -import freechips.rocketchip.util.CoreMonitorBundle -import org.chipsalliance.t1.rockettile.{AbstractLazyT1, AbstractLazyT1ModuleImp} +import freechips.rocketchip.subsystem.{BaseSubsystem, InstantiatesHierarchicalElements} import org.chipsalliance.cde.config._ +import org.chipsalliance.t1.rockettile.{AbstractLazyT1, AbstractLazyT1ModuleImp} import org.chipsalliance.t1.rtl.{V, VParameter} case object T1ConfigPath extends Field[os.Path] -trait HasT1Tiles extends HasTiles { this: BaseSubsystem => - val t1Tiles = tiles.collect { case r: org.chipsalliance.t1.rocketcore.RocketTile => r } - def coreMonitorBundles = List.empty[CoreMonitorBundle] +trait HasT1Tiles { this: BaseSubsystem with InstantiatesHierarchicalElements => + lazy val t1Tiles = totalTiles.values.collect { case r: org.chipsalliance.t1.rocketcore.RocketTile => r } } class LazyT1()(implicit p: Parameters) extends AbstractLazyT1 { diff --git a/subsystem/src/Subsystem.scala b/subsystem/src/Subsystem.scala index 03c7e8b633..32706f7dd7 100644 --- a/subsystem/src/Subsystem.scala +++ b/subsystem/src/Subsystem.scala @@ -5,17 +5,16 @@ package org.chipsalliance.t1.subsystem import chisel3._ import chisel3.experimental.UnlocatableSourceInfo -import freechips.rocketchip.devices.debug.DebugModuleKey +import freechips.rocketchip.devices.debug.{DebugModuleKey, TLDebugModule} +import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{DCacheParams, ICacheParams, MulDivParams, RocketCoreParams} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.devices.tilelink._ -import org.chipsalliance.t1.rockettile.BuildVector import freechips.rocketchip.tile.XLen import freechips.rocketchip.util.DontTouch import org.chipsalliance.cde.config._ import org.chipsalliance.t1.rocketcore.{RocketTileAttachParams, RocketTileParams} -import freechips.rocketchip.interrupts.NullIntSyncSource +import org.chipsalliance.t1.rockettile.BuildVector class VerdesConfig extends Config( @@ -38,6 +37,7 @@ class VerdesConfig case ControlBusKey => PeripheryBusParams( beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes), + dtsFrequency = Some(BigInt(1000000000)), errorDevice = Some(BuiltInErrorDeviceParams( errorParams = DevNullParams(List(AddressSet(BigInt("80003000", 16), BigInt("fff", 16))), maxAtomic=site(XLen)/8, maxTransfer=4096)))) case CLINTKey => Some(CLINTParams(BigInt("82000000", 16))) @@ -76,7 +76,7 @@ class VerdesConfig tiny, RocketCrossingParams( crossingType = SynchronousCrossing(), - master = TileMasterPortParams()) + master = HierarchicalElementMasterPortParams()) )) }) .orElse(new WithClockGateModel("./dependencies/rocket-chip/src/vsrc/EICG_wrapper.v")) @@ -93,20 +93,27 @@ class VerdesConfig ) class VerdesSystem(implicit p: Parameters) extends BaseSubsystem - with HasT1Tiles + with InstantiatesHierarchicalElements + with HasTileNotificationSinks + with HasTileInputConstants + with CanHavePeripheryCLINT + with CanHavePeripheryPLIC with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort - with HasAsyncExtInterrupts { + with HasAsyncExtInterrupts + with HasHierarchicalElementsRootContext + with HasHierarchicalElements + with HasT1Tiles { // configure val resetVectorSourceNode = BundleBridgeSource[UInt]() - tileResetVectorNexusNode := resetVectorSourceNode + tileResetVectorNodes.values.foreach(_ := resetVectorSourceNode) val resetVector = InModuleBody(resetVectorSourceNode.makeIO()) - override lazy val debugNode = NullIntSyncSource() override lazy val module = new VerdesSystemModuleImp(this) + lazy val debugOpt: Option[TLDebugModule] = None } class VerdesSystemModuleImp[+L <: VerdesSystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasTilesModuleImp + with HasHierarchicalElementsRootContextModuleImp with HasRTCModuleImp with HasExtInterruptsModuleImp with DontTouch \ No newline at end of file diff --git a/subsystememu/src/Testbench.scala b/subsystememu/src/Testbench.scala index a2fa337b0f..d6067f3340 100644 --- a/subsystememu/src/Testbench.scala +++ b/subsystememu/src/Testbench.scala @@ -25,13 +25,12 @@ class TestHarness(implicit val p: Parameters) extends RawModule { withClockAndReset(clock.asClock, reset) { val dut = Module(ldut.module) // Allow the debug ndreset to reset the dut, but not until the initial reset has completed - dut.reset := reset.asBool dut.interrupts := 0.U dut.dontTouchPorts() ldut.resetVector := dpiResetVector.resetVector.ref - dpiResetVector.reset.ref := dut.reset - dpiResetVector.clock.ref := dut.clock.asBool + dpiResetVector.reset.ref := reset + dpiResetVector.clock.ref := clock ldut.mem_axi4.zip(ldut.memAXI4Node.in).map { case (io, (_, edge)) => val mem = LazyModule(new LazyAXI4MemBFM(edge, base = p(ExtMem).get.master.base, size = p(ExtMem).get.master.size)) Module(mem.module).suggestName("mem") diff --git a/t1/src/VectorFunctionUnit.scala b/t1/src/VectorFunctionUnit.scala index 9ad8e4e35b..bffab219d1 100644 --- a/t1/src/VectorFunctionUnit.scala +++ b/t1/src/VectorFunctionUnit.scala @@ -4,7 +4,7 @@ package org.chipsalliance.t1.rtl import chisel3._ -import chisel3.experimental.{AutoCloneType, SerializableModuleGenerator} +import chisel3.experimental.{SerializableModuleGenerator} import chisel3.properties.Property import org.chipsalliance.t1.rtl.decoder.BoolField import chisel3.util._ @@ -77,7 +77,7 @@ case class VFUInstantiateParameter( } class SlotExecuteRequest[T <: SlotRequestToVFU](requestFromSlot: T)(slotIndex: Int, parameter: VFUInstantiateParameter) - extends Record with AutoCloneType { + extends Record { val elements: SeqMap[String, DecoupledIO[SlotRequestToVFU]] = SeqMap.from( parameter.genVec.filter(_._2.contains(slotIndex)).map { case (p, _) => p.parameter.decodeField.name -> Decoupled(requestFromSlot)