From 3fb958ac7d7e2a54e524f5fb4b888edc7a677dda Mon Sep 17 00:00:00 2001 From: Lucas-Wye Date: Sun, 23 Jun 2024 19:35:09 +0800 Subject: [PATCH] [doc] add missing zero uop and fix error of some attributes --- t1/src/decoder/Decoder.scala | 21 +-- t1/src/decoder/T1DecodePattern.scala | 1 + t1/src/decoder/attribute/adderUop.scala | 30 ++-- t1/src/decoder/attribute/divUop.scala | 2 +- t1/src/decoder/attribute/floatUop.scala | 14 +- t1/src/decoder/attribute/isAverage.scala | 48 ++++++- t1/src/decoder/attribute/isCrosswrite.scala | 48 ++++++- t1/src/decoder/attribute/isFloat.scala | 16 +-- t1/src/decoder/attribute/isMv.scala | 8 +- t1/src/decoder/attribute/isSaturate.scala | 48 ++++++- t1/src/decoder/attribute/isSpecial.scala | 140 +++++++++---------- t1/src/decoder/attribute/isWidenreduce.scala | 48 ++++++- t1/src/decoder/attribute/isZero.scala | 55 ++++++++ t1/src/decoder/attribute/mulUop.scala | 8 +- t1/src/decoder/attribute/uop.scala | 3 +- t1/src/decoder/attribute/zeroUop.scala | 45 ++++++ 16 files changed, 413 insertions(+), 122 deletions(-) create mode 100644 t1/src/decoder/attribute/isZero.scala create mode 100644 t1/src/decoder/attribute/zeroUop.scala diff --git a/t1/src/decoder/Decoder.scala b/t1/src/decoder/Decoder.scala index 794c8f3802..e569953e9d 100644 --- a/t1/src/decoder/Decoder.scala +++ b/t1/src/decoder/Decoder.scala @@ -215,14 +215,14 @@ object Decoder { object topUop extends T1UopField { override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop.value match { - case _: TopT0.type => BitPat("b0000") - case _: TopT1.type => BitPat("b0001") - case _: TopT2.type => BitPat("b0010") - case _: TopT3.type => BitPat("b0011") - case _: TopT5.type => BitPat("b0101") - case _: TopT6.type => BitPat("b0110") - case _: TopT7.type => BitPat("b0111") - case _ => BitPat.dontCare(4) + case _: TopT0.type => BitPat("b000") + case _: TopT1.type => BitPat("b001") + case _: TopT2.type => BitPat("b010") + case _: TopT3.type => BitPat("b011") + case _: TopT5.type => BitPat("b101") + case _: TopT6.type => BitPat("b110") + case _: TopT7.type => BitPat("b111") + case _ => BitPat.dontCare(3) } } @@ -315,6 +315,11 @@ object Decoder { case _: shiftUop6.type => BitPat("b0110") case _ => BitPat.dontCare(4) } + case zeroCase: ZeroUOPType => + zeroCase match { + case _: zeroUop0.type => BitPat("b0000") + case _ => BitPat.dontCare(4) + } case _ => BitPat.dontCare(4) } } diff --git a/t1/src/decoder/T1DecodePattern.scala b/t1/src/decoder/T1DecodePattern.scala index 2a0da9d74d..3d53a111ba 100644 --- a/t1/src/decoder/T1DecodePattern.scala +++ b/t1/src/decoder/T1DecodePattern.scala @@ -88,6 +88,7 @@ case class T1DecodePattern(instruction: Instruction, param: DecoderParam) extend def isNr: isNr = attribute.isNr(this) def isOrderreduce: isOrderreduce = attribute.isOrderreduce(this) def isOther: isOther = attribute.isOther(this) + def isZero: isZero = attribute.isZero(this) def isPopcount: isPopcount = attribute.isPopcount(this) def isReadonly: isReadonly = attribute.isReadonly(this) def isRed: isRed = attribute.isRed(this) diff --git a/t1/src/decoder/attribute/adderUop.scala b/t1/src/decoder/attribute/adderUop.scala index 468c1731fb..19c268b178 100644 --- a/t1/src/decoder/attribute/adderUop.scala +++ b/t1/src/decoder/attribute/adderUop.scala @@ -87,21 +87,21 @@ object AdderUOP { "vwsubu.vx", "vwsubu.wv", "vwsubu.wx", - "vadc.vim", - "vadc.vvm", - "vadc.vxm", - "vmadc.vi", - "vmadc.vim", - "vmadc.vv", - "vmadc.vvm", - "vmadc.vx", - "vmadc.vxm", - "vmsbc.vv", - "vmsbc.vvm", - "vmsbc.vx", - "vmsbc.vxm", - "vsbc.vvm", - "vsbc.vxm", + // "vadc.vim", + // "vadc.vvm", + // "vadc.vxm", + // "vmadc.vi", + // "vmadc.vim", + // "vmadc.vv", + // "vmadc.vvm", + // "vmadc.vx", + // "vmadc.vxm", + // "vmsbc.vv", + // "vmsbc.vvm", + // "vmsbc.vx", + // "vmsbc.vxm", + // "vsbc.vvm", + // "vsbc.vxm", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/divUop.scala b/t1/src/decoder/attribute/divUop.scala index 54a7a84b12..df8b078d24 100644 --- a/t1/src/decoder/attribute/divUop.scala +++ b/t1/src/decoder/attribute/divUop.scala @@ -39,7 +39,7 @@ object DivUOP { "vrem.vx", "vremu.vv", "vremu.vx", - "vfrdiv.vf", + // "vfrdiv.vf", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/floatUop.scala b/t1/src/decoder/attribute/floatUop.scala index 7ee40cb514..652925372f 100644 --- a/t1/src/decoder/attribute/floatUop.scala +++ b/t1/src/decoder/attribute/floatUop.scala @@ -69,13 +69,13 @@ object FloatUop { "vfsgnj.vv", "vmfeq.vf", "vmfeq.vv", - "vfcvt.x.f.v", - "vfmax.vf", - "vfmax.vv", - "vfredmax.vs", - "vfcvt.rtz.xu.f.v", - "vfrsub.vf", - "vfcvt.rtz.x.f.v", + // "vfcvt.x.f.v", + // "vfmax.vf", + // "vfmax.vv", + // "vfredmax.vs", + // "vfcvt.rtz.xu.f.v", + // "vfrsub.vf", + // "vfcvt.rtz.x.f.v", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/isAverage.scala b/t1/src/decoder/attribute/isAverage.scala index 0d52502e07..8763aeaa56 100644 --- a/t1/src/decoder/attribute/isAverage.scala +++ b/t1/src/decoder/attribute/isAverage.scala @@ -35,7 +35,53 @@ object isAverage { allMatched.contains(t1DecodePattern.instruction) } - def dc(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } } case class isAverage(value: TriState) extends BooleanDecodeAttribute { diff --git a/t1/src/decoder/attribute/isCrosswrite.scala b/t1/src/decoder/attribute/isCrosswrite.scala index 7523e6176a..cbe920dbba 100644 --- a/t1/src/decoder/attribute/isCrosswrite.scala +++ b/t1/src/decoder/attribute/isCrosswrite.scala @@ -56,7 +56,53 @@ object isCrosswrite { allMatched.contains(t1DecodePattern.instruction) } - def dc(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } } case class isCrosswrite(value: TriState) extends BooleanDecodeAttribute { diff --git a/t1/src/decoder/attribute/isFloat.scala b/t1/src/decoder/attribute/isFloat.scala index 65eb6d35e6..9f4e6bcc52 100644 --- a/t1/src/decoder/attribute/isFloat.scala +++ b/t1/src/decoder/attribute/isFloat.scala @@ -26,15 +26,15 @@ object isFloat { "vfcvt.rtz.xu.f.v", "vfcvt.x.f.v", "vfcvt.xu.f.v", - "vfdiv.vf", - "vfdiv.vv", + // "vfdiv.vf", + // "vfdiv.vv", "vfmacc.vf", "vfmacc.vv", "vfmadd.vf", "vfmadd.vv", "vfmax.vf", "vfmax.vv", - "vfmerge.vfm", + // "vfmerge.vfm", "vfmin.vf", "vfmin.vv", "vfmsac.vf", @@ -44,7 +44,7 @@ object isFloat { "vfmul.vf", "vfmul.vv", "vfmv.f.s", - "vfmv.s.f", + // "vfmv.s.f", "vfncvt.f.f.w", "vfncvt.f.x.w", "vfncvt.f.xu.w", @@ -61,7 +61,7 @@ object isFloat { "vfnmsac.vv", "vfnmsub.vf", "vfnmsub.vv", - "vfrdiv.vf", + // "vfrdiv.vf", "vfrec7.v", "vfredmax.vs", "vfredmin.vs", @@ -75,9 +75,9 @@ object isFloat { "vfsgnjn.vv", "vfsgnjx.vf", "vfsgnjx.vv", - "vfslide1down.vf", - "vfslide1up.vf", - "vfsqrt.v", + // "vfslide1down.vf", + // "vfslide1up.vf", + // "vfsqrt.v", "vfsub.vf", "vfsub.vv", "vfwadd.vf", diff --git a/t1/src/decoder/attribute/isMv.scala b/t1/src/decoder/attribute/isMv.scala index 75fb59ecf7..ab3c044523 100644 --- a/t1/src/decoder/attribute/isMv.scala +++ b/t1/src/decoder/attribute/isMv.scala @@ -21,10 +21,10 @@ object isMv { "vfmv.s.f", "vmv.s.x", "vmv.x.s", - "vmv1r.v", - "vmv2r.v", - "vmv4r.v", - "vmv8r.v", + // "vmv1r.v", + // "vmv2r.v", + // "vmv4r.v", + // "vmv8r.v", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/isSaturate.scala b/t1/src/decoder/attribute/isSaturate.scala index a9a5287dcd..4440816e4d 100644 --- a/t1/src/decoder/attribute/isSaturate.scala +++ b/t1/src/decoder/attribute/isSaturate.scala @@ -54,7 +54,53 @@ object isSaturate { allMatched.contains(t1DecodePattern.instruction) } - def dc(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } } case class isSaturate(value: TriState) extends BooleanDecodeAttribute { diff --git a/t1/src/decoder/attribute/isSpecial.scala b/t1/src/decoder/attribute/isSpecial.scala index 81b5ebf3c5..2fc7259d57 100644 --- a/t1/src/decoder/attribute/isSpecial.scala +++ b/t1/src/decoder/attribute/isSpecial.scala @@ -17,35 +17,35 @@ object isSpecial { def y(t1DecodePattern: T1DecodePattern): Boolean = { val allMatched = Seq( - "vadc.vim", - "vadc.vvm", - "vadc.vxm", + // "vadc.vim", + // "vadc.vvm", + // "vadc.vxm", "vcompress.vm", "vcpop.m", "vfirst.m", - "vfmerge.vfm", + // "vfmerge.vfm", "vfmv.f.s", "vfmv.s.f", - "vfncvt.f.f.w", - "vfncvt.f.x.w", - "vfncvt.f.xu.w", - "vfncvt.rod.f.f.w", - "vfncvt.rtz.x.f.w", - "vfncvt.rtz.xu.f.w", - "vfncvt.x.f.w", - "vfncvt.xu.f.w", + // "vfncvt.f.f.w", + // "vfncvt.f.x.w", + // "vfncvt.f.xu.w", + // "vfncvt.rod.f.f.w", + // "vfncvt.rtz.x.f.w", + // "vfncvt.rtz.xu.f.w", + // "vfncvt.x.f.w", + // "vfncvt.xu.f.w", "vfredmax.vs", "vfredmin.vs", "vfredosum.vs", "vfredusum.vs", "vfslide1down.vf", "vfslide1up.vf", - "vfwadd.wf", - "vfwadd.wv", + // "vfwadd.wf", + // "vfwadd.wv", "vfwredosum.vs", "vfwredusum.vs", - "vfwsub.wf", - "vfwsub.wv", + // "vfwsub.wf", + // "vfwsub.wv", "viota.m", "vloxei1024.v", "vloxei128.v", @@ -69,11 +69,11 @@ object isSpecial { "vmadc.vvm", "vmadc.vx", "vmadc.vxm", - "vmand.mm", - "vmandn.mm", - "vmerge.vim", - "vmerge.vvm", - "vmerge.vxm", + // "vmand.mm", + // "vmandn.mm", + // "vmerge.vim", + // "vmerge.vvm", + // "vmerge.vxm", "vmfeq.vf", "vmfeq.vv", "vmfge.vf", @@ -84,10 +84,10 @@ object isSpecial { "vmflt.vv", "vmfne.vf", "vmfne.vv", - "vmnand.mm", - "vmnor.mm", - "vmor.mm", - "vmorn.mm", + // "vmnand.mm", + // "vmnor.mm", + // "vmor.mm", + // "vmorn.mm", "vmsbc.vv", "vmsbc.vvm", "vmsbc.vx", @@ -117,20 +117,20 @@ object isSpecial { "vmsof.m", "vmv.s.x", "vmv.x.s", - "vmxnor.mm", - "vmxor.mm", - "vnclip.wi", - "vnclip.wv", - "vnclip.wx", - "vnclipu.wi", - "vnclipu.wv", - "vnclipu.wx", - "vnsra.wi", - "vnsra.wv", - "vnsra.wx", - "vnsrl.wi", - "vnsrl.wv", - "vnsrl.wx", + // "vmxnor.mm", + // "vmxor.mm", + // "vnclip.wi", + // "vnclip.wv", + // "vnclip.wx", + // "vnclipu.wi", + // "vnclipu.wv", + // "vnclipu.wx", + // "vnsra.wi", + // "vnsra.wv", + // "vnsra.wx", + // "vnsrl.wi", + // "vnsrl.wv", + // "vnsrl.wx", "vredand.vs", "vredmax.vs", "vredmaxu.vs", @@ -141,8 +141,8 @@ object isSpecial { "vredxor.vs", "vrgather.vv", "vrgatherei16.vv", - "vsbc.vvm", - "vsbc.vxm", + // "vsbc.vvm", + // "vsbc.vxm", "vsext.vf2", "vsext.vf4", "vsext.vf8", @@ -168,37 +168,37 @@ object isSpecial { "vsuxei512.v", "vsuxei64.v", "vsuxei8.v", - "vwadd.vv", - "vwadd.vx", - "vwadd.wv", - "vwadd.wx", - "vwaddu.vv", - "vwaddu.vx", - "vwaddu.wv", - "vwaddu.wx", - "vwmacc.vv", - "vwmacc.vx", - "vwmaccsu.vv", - "vwmaccsu.vx", - "vwmaccu.vv", - "vwmaccu.vx", - "vwmaccus.vx", - "vwmul.vv", - "vwmul.vx", - "vwmulsu.vv", - "vwmulsu.vx", - "vwmulu.vv", - "vwmulu.vx", + // "vwadd.vv", + // "vwadd.vx", + // "vwadd.wv", + // "vwadd.wx", + // "vwaddu.vv", + // "vwaddu.vx", + // "vwaddu.wv", + // "vwaddu.wx", + // "vwmacc.vv", + // "vwmacc.vx", + // "vwmaccsu.vv", + // "vwmaccsu.vx", + // "vwmaccu.vv", + // "vwmaccu.vx", + // "vwmaccus.vx", + // "vwmul.vv", + // "vwmul.vx", + // "vwmulsu.vv", + // "vwmulsu.vx", + // "vwmulu.vv", + // "vwmulu.vx", "vwredsum.vs", "vwredsumu.vs", - "vwsub.vv", - "vwsub.vx", - "vwsub.wv", - "vwsub.wx", - "vwsubu.vv", - "vwsubu.vx", - "vwsubu.wv", - "vwsubu.wx", + // "vwsub.vv", + // "vwsub.vx", + // "vwsub.wv", + // "vwsub.wx", + // "vwsubu.vv", + // "vwsubu.vx", + // "vwsubu.wv", + // "vwsubu.wx", "vzext.vf2", "vzext.vf4", "vzext.vf8", diff --git a/t1/src/decoder/attribute/isWidenreduce.scala b/t1/src/decoder/attribute/isWidenreduce.scala index 4902238806..8815b4a2e7 100644 --- a/t1/src/decoder/attribute/isWidenreduce.scala +++ b/t1/src/decoder/attribute/isWidenreduce.scala @@ -29,7 +29,53 @@ object isWidenreduce { allMatched.contains(t1DecodePattern.instruction) } - def dc(t1DecodePattern: T1DecodePattern): Boolean = false + def dc(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcpop.m", + "vfclass.v", + "vfcvt.f.x.v", + "vfcvt.f.xu.v", + "vfcvt.rtz.x.f.v", + "vfcvt.rtz.xu.f.v", + "vfcvt.x.f.v", + "vfcvt.xu.f.v", + "vfirst.m", + "vfmv.f.s", + "vfmv.s.f", + "vfncvt.f.f.w", + "vfncvt.f.x.w", + "vfncvt.f.xu.w", + "vfncvt.rod.f.f.w", + "vfncvt.rtz.x.f.w", + "vfncvt.rtz.xu.f.w", + "vfncvt.x.f.w", + "vfncvt.xu.f.w", + "vfrec7.v", + "vfrsqrt7.v", + "vfsqrt.v", + "vfwcvt.f.f.v", + "vfwcvt.f.x.v", + "vfwcvt.f.xu.v", + "vfwcvt.rtz.x.f.v", + "vfwcvt.rtz.xu.f.v", + "vfwcvt.x.f.v", + "vfwcvt.xu.f.v", + "vid.v", + "viota.m", + "vmsbf.m", + "vmsif.m", + "vmsof.m", + "vmv.s.x", + "vmv.x.s", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } } case class isWidenreduce(value: TriState) extends BooleanDecodeAttribute { diff --git a/t1/src/decoder/attribute/isZero.scala b/t1/src/decoder/attribute/isZero.scala new file mode 100644 index 0000000000..8017ebf56e --- /dev/null +++ b/t1/src/decoder/attribute/isZero.scala @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +object isZero { + def apply(t1DecodePattern: T1DecodePattern): isZero = + Seq( + y _ -> Y, + n _ -> N, + dc _ -> DC + ).collectFirst { + case (fn, tri) if fn(t1DecodePattern) => isZero(tri) + }.get + + def y(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = Seq( + "vcompress.vm", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def n(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched = t1DecodePattern.param.allInstructions.filter(i => + !(y(t1DecodePattern) || dc(t1DecodePattern)) + ) + allMatched.contains(t1DecodePattern.instruction) + } + + def dc(t1DecodePattern: T1DecodePattern): Boolean = false +} + +case class isZero(value: TriState) extends BooleanDecodeAttribute { + override val description: String = "goes to [[org.chipsalliance.t1.rtl.OtherUnit]]" +} diff --git a/t1/src/decoder/attribute/mulUop.scala b/t1/src/decoder/attribute/mulUop.scala index a498af695c..756c664a0c 100644 --- a/t1/src/decoder/attribute/mulUop.scala +++ b/t1/src/decoder/attribute/mulUop.scala @@ -45,10 +45,10 @@ object MulUOP { val allMatched: Seq[String] = Seq( "vmadd.vv", "vmadd.vx", - "vnmsub.vv", - "vnmsub.vx", - "vnmsac.vv", - "vnmsac.vx", + // "vnmsub.vv", + // "vnmsub.vx", + // "vnmsac.vv", + // "vnmsac.vx", ) allMatched.contains(t1DecodePattern.instruction.name) } diff --git a/t1/src/decoder/attribute/uop.scala b/t1/src/decoder/attribute/uop.scala index 82df29ab25..66d8dbf02c 100644 --- a/t1/src/decoder/attribute/uop.scala +++ b/t1/src/decoder/attribute/uop.scala @@ -14,7 +14,8 @@ object DecoderUop { isAdder.y(t1DecodePattern) -> AdderUOP(t1DecodePattern), isLogic.y(t1DecodePattern) -> LogicUop(t1DecodePattern), isShift.y(t1DecodePattern) -> ShiftUop(t1DecodePattern), - isOther.y(t1DecodePattern) -> OtherUop(t1DecodePattern) + isOther.y(t1DecodePattern) -> OtherUop(t1DecodePattern), + isZero.y(t1DecodePattern) -> ZeroUOP(t1DecodePattern) ).collectFirst { case (fn, tpe) if fn => DecoderUop(tpe) } diff --git a/t1/src/decoder/attribute/zeroUop.scala b/t1/src/decoder/attribute/zeroUop.scala new file mode 100644 index 0000000000..3c009614e1 --- /dev/null +++ b/t1/src/decoder/attribute/zeroUop.scala @@ -0,0 +1,45 @@ + +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait ZeroUOPType extends Uop +object zeroUop0 extends ZeroUOPType + +object ZeroUOP { + def apply(t1DecodePattern: T1DecodePattern): Uop = { + Seq( + t0 _ -> zeroUop0, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => tpe + }.getOrElse(UopDC) + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vcompress.vm", + "vfslide1down.vf", + "vfslide1up.vf", + "viota.m", + "vmv1r.v", + "vmv2r.v", + "vmv4r.v", + "vmv8r.v", + "vsext.vf2", + "vsext.vf4", + "vsext.vf8", + "vslide1down.vx", + "vslide1up.vx", + "vslidedown.vi", + "vslidedown.vx", + "vslideup.vi", + "vslideup.vx", + "vzext.vf2", + "vzext.vf4", + "vzext.vf8", + ) + allMatched.contains(t1DecodePattern.instruction.name) + } +}