From 2e56ed15c0f1e65421ff9f67c6fd90a0d4bed826 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Wed, 20 Nov 2024 00:45:15 +0800 Subject: [PATCH] [config] fix rookidee dlen --- .../org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml | 2 +- .../org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml index 1d92fc61e..a220f52f7 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml @@ -1,5 +1,5 @@ [rookidee] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" diff --git a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml index 1ef6a61be..1ec2949c7 100644 --- a/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml +++ b/designs/org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile.toml @@ -1,5 +1,5 @@ [rookidee] -cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" +cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_v --instructionSets zve32x --instructionSets zvl512b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 128 --vrfBankSize 2 --vrfRamType p0rwp1rw --vfuInstantiateParameter small" [blastoise] cmdopt = "--instructionSets rv32_i --instructionSets rv_m --instructionSets rv_a --instructionSets rv_c --instructionSets rv_f --instructionSets rv_v --instructionSets zve32f --instructionSets zvl2048b --cacheBlockBytes 32 --nPMPs 8 --cacheable 11111111111111111111111111111111 --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 4 --vrfRamType p0rwp1rw --vfuInstantiateParameter small"