From 2212fc74134387849e09ec04557fd6bf10310661 Mon Sep 17 00:00:00 2001 From: Clo91eaf Date: Sun, 25 Aug 2024 17:32:09 +0800 Subject: [PATCH] [t1rocket] refactor idx log --- t1rocketemu/offline/src/json_events.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/t1rocketemu/offline/src/json_events.rs b/t1rocketemu/offline/src/json_events.rs index 181429d24..b9cb3181d 100644 --- a/t1rocketemu/offline/src/json_events.rs +++ b/t1rocketemu/offline/src/json_events.rs @@ -202,7 +202,7 @@ impl JsonEventRunner for SpikeRunner { if let Some(board_data) = self.rf_board[idx as usize] { info!( - "[{cycle}] RegWrite: Hit board! idx={idx}, rtl data={data:#08x}, board data={board_data:#08x}", + "[{cycle}] RegWrite: Hit board! idx={idx}, rtl data={data:#x}, board data={board_data:#x}", ); assert!( @@ -218,7 +218,7 @@ impl JsonEventRunner for SpikeRunner { let se = self.find_reg_se(); info!( - "[{cycle}] RegWrite: rtl idx={idx}, data={data:#08x}; se idx={}, data={:#08x} ({})", + "[{cycle}] RegWrite: rtl idx={idx}, data={data:#x}; se idx={}, data={:#x} ({})", se.rd_idx, se.rd_bits, se.describe_insn() @@ -226,7 +226,7 @@ impl JsonEventRunner for SpikeRunner { assert!( idx as u32 == se.rd_idx, - "rtl idx({idx:#x}) should be equal to spike idx({:#x})", + "rtl idx({idx}) should be equal to spike idx({})", se.rd_idx ); assert!( @@ -245,7 +245,7 @@ impl JsonEventRunner for SpikeRunner { let se = self.find_reg_se(); info!( - "[{cycle}] RegWriteWait: rtl idx={idx}; se idx={}, data={:#08x} ({})", + "[{cycle}] RegWriteWait: rtl idx={idx}; se idx={}, data={:#x} ({})", se.rd_idx, se.rd_bits, se.describe_insn() @@ -253,7 +253,7 @@ impl JsonEventRunner for SpikeRunner { assert!( idx as u32 == se.rd_idx, - "rtl idx({idx:#x}) should be equal to spike idx({:#x})", + "rtl idx({idx}) should be equal to spike idx({})", se.rd_idx ); @@ -271,7 +271,7 @@ impl JsonEventRunner for SpikeRunner { if let Some(board_data) = self.frf_board[idx as usize] { info!( - "[{cycle}] FregWrite: Hit board! idx={idx}, rtl data={data:#08x}, board data={board_data:#08x}", + "[{cycle}] FregWrite: Hit board! idx={idx}, rtl data={data:#x}, board data={board_data:#x}", ); assert!( @@ -285,7 +285,7 @@ impl JsonEventRunner for SpikeRunner { } info!( - "[{cycle}] FregWrite: rtl idx={idx}, data={data:#08x}; se idx={}, data={:#08x} ({})", + "[{cycle}] FregWrite: rtl idx={idx}, data={data:#x}; se idx={}, data={:#x} ({})", se.rd_idx, se.rd_bits, se.describe_insn() @@ -293,7 +293,7 @@ impl JsonEventRunner for SpikeRunner { assert!( idx as u32 == se.rd_idx, - "rtl idx({idx:#x}) should be equal to spike idx({:#x})", + "rtl idx({idx}) should be equal to spike idx({})", se.rd_idx ); assert!( @@ -312,7 +312,7 @@ impl JsonEventRunner for SpikeRunner { let se = self.find_freg_se(); info!( - "[{cycle}] RegWriteWait: rtl idx={idx}; se idx={}, data={:#08x} ({})", + "[{cycle}] FregWriteWait: rtl idx={idx}; se idx={}, data={:#x} ({})", se.rd_idx, se.rd_bits, se.describe_insn() @@ -320,7 +320,7 @@ impl JsonEventRunner for SpikeRunner { assert!( idx as u32 == se.rd_idx, - "rtl idx({idx:#x}) should be equal to spike idx({:#x})", + "rtl idx({idx}) should be equal to spike idx({})", se.rd_idx ); @@ -467,7 +467,7 @@ impl JsonEventRunner for SpikeRunner { let lsu_idx = memory_write.lsu_idx; if let Some(se) = self.commit_queue.iter_mut().find(|se| se.lsu_idx == lsu_idx) { - info!("[{cycle}] MemoryWrite: address={base_addr:#08x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm); + info!("[{cycle}] MemoryWrite: address={base_addr:#x}, size={}, data={data:x?}, mask={}, pc = {:#x}, disasm = {}", data.len(), mask_display(&mask), se.pc, se.disasm); // compare with spike event record mask.iter().enumerate() .filter(|(_, &mask)| mask) @@ -476,11 +476,11 @@ impl JsonEventRunner for SpikeRunner { let data_byte = *data.get(offset).unwrap_or(&0); let mem_write = se.mem_access_record.all_writes.get_mut(&byte_addr).unwrap_or_else(|| { - panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:#08x}") + panic!("[{cycle}] cannot find mem write of byte_addr {byte_addr:#x}") }); let single_mem_write_val = mem_write.writes[mem_write.num_completed_writes].val; mem_write.num_completed_writes += 1; - assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:#02x}, actual byte {data_byte:#02x} (byte_addr={byte_addr:#08x}, pc = {:#x}, disasm = {})", se.pc, se.disasm); + assert_eq!(single_mem_write_val, data_byte, "[{cycle}] expect mem write of byte {single_mem_write_val:#02x}, actual byte {data_byte:#02x} (byte_addr={byte_addr:#x}, pc = {:#x}, disasm = {})", se.pc, se.disasm); }); return Ok(()); }