From 203c59f7316f1e5b9a69427f4ebc5932a076f47a Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Wed, 29 May 2024 17:17:18 +0800 Subject: [PATCH] [rtl] Use token to manage the vrf status of instructions.(wip) --- t1/src/Bundles.scala | 23 ++++----- t1/src/Lane.scala | 118 ++++++++++++------------------------------- t1/src/T1.scala | 19 +++---- t1/src/vrf/VRF.scala | 51 +++++++++---------- 4 files changed, 72 insertions(+), 139 deletions(-) diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala index cc2ef7ece6..07f4e4e5a7 100644 --- a/t1/src/Bundles.scala +++ b/t1/src/Bundles.scala @@ -64,13 +64,6 @@ class InstructionRecord(instructionIndexWidth: Int) extends Bundle { */ val instructionIndex: UInt = UInt(instructionIndexWidth.W) - /** whether instruction need wait for write queue clear, - * for instructions has `widen`, it need use cross lane write channel, - * but lane will regard the instruction is finished when data is sent to ring, - * so we need this bit to record if the ring is cleared. - */ - val needWaitWriteQueueClear: Bool = Bool() - /** whether instruction is load store. * it should tell scalar core if this is a load store unit. */ @@ -470,6 +463,14 @@ class LSUWriteCheck(regNumBits: Int, offsetBits: Int, instructionIndexSize: Int) val instructionIndex: UInt = UInt(instructionIndexSize.W) } +class VRFInstructionState extends Bundle { + val stFinish: Bool = Bool() + // execute finish, wait for write queue clear + val wWriteQueueClear: Bool = Bool() + val wLaneLastReport: Bool = Bool() + val wLaneClear: Bool = Bool() +} + class VRFWriteReport(param: VRFParam) extends Bundle { // 8 reg/group; which group? val vd: ValidIO[UInt] = Valid(UInt(param.regNumBits.W)) @@ -482,15 +483,8 @@ class VRFWriteReport(param: VRFParam) extends Bundle { val crossWrite: Bool = Bool() // instruction will cross read val crossRead: Bool = Bool() - val stFinish: Bool = Bool() // index type lsu val indexType: Bool = Bool() - // execute finish, wait for write queue clear - val wWriteQueueClear: Bool = Bool() - // wait cross write bus clear - val wBusClear = Bool() - // wait cross write queue clear - val wQueueClear = Bool() // 乘加 val ma: Bool = Bool() // 慢指令 mask unit @@ -498,6 +492,7 @@ class VRFWriteReport(param: VRFParam) extends Bundle { // which element will access(write or store read) // true: No access or access has been completed val elementMask: UInt = UInt(param.elementSize.W) + val state = new VRFInstructionState } /** 为了decode, 指令需要在入口的时候打一拍, 这是需要保存的信息 */ diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index 38e98ee2ce..d762209ff6 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -289,10 +289,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ @public val loadDataInLSUWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W))) - /** for RaW, VRF should wait for cross write bus to be empty. */ - @public - val dataInCrossBus: UInt = IO(Input(UInt(parameter.chainingSize.W))) - /** How many dataPath will writ by instruction in this lane */ @public val writeCount: UInt = @@ -303,8 +299,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val writeReadyForLsu: Bool = IO(Output(Bool())) @public val vrfReadyToStore: Bool = IO(Output(Bool())) - @public - val crossWriteDataInSlot: UInt = IO(Output(UInt(parameter.chainingSize.W))) @public val probe: LaneProbe = IO(Output(Probe(new LaneProbe(parameter.chainingSize)))) @@ -349,9 +343,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val maskIndexVec: Vec[UInt] = RegInit(VecInit(Seq.fill(parameter.chainingSize)(0.U(log2Ceil(parameter.maskGroupWidth).W)))) - /** pipe state for slot */ - val pipeFinishVec: Vec[Bool] = RegInit(VecInit(Seq.fill(parameter.chainingSize)(false.B))) - /** the find first one index register in this lane. */ val ffoIndexReg: UInt = RegInit(0.U(log2Ceil(parameter.vLen / 8).W)) @@ -488,11 +479,9 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val slot0EnqueueFire: Bool = Wire(Bool()) - /** assert when a instruction is finished in the slot. */ - val instructionFinishedVec: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.chainingSize.W))) - - /** any cross lane write data in slot */ - val crossWriteDataInSlotVec: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.chainingSize.W))) + /** assert when a instruction is valid in the slot. */ + val instructionValid: UInt = Wire(UInt(parameter.chainingSize.W)) + val instructionValidNext: UInt = RegNext(instructionValid, 0.U) /** assert when a instruction will not use mask unit */ val instructionUnrelatedMaskUnitVec: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.chainingSize.W))) @@ -514,9 +503,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ )) val maskedWriteUnit: Instance[MaskedWrite] = Instantiate(new MaskedWrite(parameter)) val tokenManager: Instance[SlotTokenManager] = Instantiate(new SlotTokenManager(parameter)) - val dataInPipeQueue: UInt = Wire(UInt(parameter.chainingSize.W)) - // data in allVrfWriteAfterCheck - val dataInAfterCheck: UInt = Wire(UInt(parameter.chainingSize.W)) slotControl.zipWithIndex.foreach { case (record, index) => val decodeResult: DecodeBundle = record.laneRequest.decodeResult @@ -550,21 +536,19 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ // register for s0 enqueue, it will move with the slot // 'maskGroupCountVec' 'maskIndexVec' 'pipeFinishVec' - // pipe clear - val pipeClear: Bool = Wire(Bool()) - if (isLastSlot) { - slotActive(index) := slotOccupied(index) && !pipeFinishVec(index) + // todo: Reach vfu + slotActive(index) := slotOccupied(index) } else { - slotActive(index) := slotOccupied(index) && !pipeFinishVec(index) && !slotShiftValid(index) && + slotActive(index) := slotOccupied(index) && !slotShiftValid(index) && !(decodeResult(Decoder.crossRead) || decodeResult(Decoder.crossWrite) || decodeResult(Decoder.widenReduce)) && decodeResult(Decoder.scheduler) } if(isLastSlot) { - slotCanShift(index) := pipeClear && pipeFinishVec(index) + slotCanShift(index) := !slotOccupied(index) } else { - slotCanShift(index) := pipeClear + slotCanShift(index) := true.B } val laneState: LaneState = Wire(new LaneState(parameter)) @@ -612,7 +596,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ // todo: handle all elements in first group are masked maskIndexVec(index) := stage0.updateLaneState.maskIndex when(stage0.updateLaneState.outOfExecutionRange) { - pipeFinishVec(index) := true.B + slotOccupied(index) := false.B } } @@ -636,17 +620,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ val instructionIndex1H: UInt = UIntToOH( record.laneRequest.instructionIndex(parameter.instructionIndexBits - 2, 0) ) - instructionFinishedVec(index) := 0.U instructionUnrelatedMaskUnitVec(index) := Mux(decodeResult(Decoder.maskUnit) && decodeResult(Decoder.readOnly), 0.U, instructionIndex1H) - val dataInWritePipe: Bool = - ohCheck(maskedWriteUnit.maskedWrite1H, record.laneRequest.instructionIndex, parameter.chainingSize) | - ohCheck(dataInPipeQueue, record.laneRequest.instructionIndex, parameter.chainingSize) | - ohCheck(dataInAfterCheck, record.laneRequest.instructionIndex, parameter.chainingSize) - when(slotOccupied(index) && pipeClear && pipeFinishVec(index) && !dataInWritePipe) { - slotOccupied(index) := false.B - instructionFinishedVec(index) := instructionIndex1H - } // stage 1: read stage stage1.enqueue.valid := stage0.dequeue.valid @@ -714,12 +689,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ } } - crossWriteDataInSlotVec(index) := Mux( - (pipeClear & !slotOccupied(index)) || !decodeResult(Decoder.crossWrite), - 0.U, - indexToOH(record.laneRequest.instructionIndex, parameter.chainingSize) - ) - stage2.enqueue.valid := stage1.dequeue.valid && executionUnit.enqueue.ready stage1.dequeue.ready := stage2.enqueue.ready && executionUnit.enqueue.ready executionUnit.enqueue.valid := stage1.dequeue.valid && stage2.enqueue.ready @@ -814,7 +783,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ vrfWriteArbiter(index).bits := stage3.vrfWriteRequest.bits stage3.vrfWriteRequest.ready := vrfWriteArbiter(index).ready - pipeClear := !Seq(stage0.stageValid, stage1.stageValid, stage2.stageValid, stage3.stageValid, dataInWritePipe).reduce(_ || _) tokenManager.enqReports(index) := stage0.tokenReport // probes @@ -823,7 +791,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ probeWire.slots(index).changingMaskSet := record.mask.valid || !record.laneRequest.mask probeWire.slots(index).slotActive := slotActive(index) probeWire.slots(index).slotOccupied := slotOccupied(index) - probeWire.slots(index).pipeFinish := pipeFinishVec(index) + probeWire.slots(index).pipeFinish := !slotOccupied(index) probeWire.slots(index).slotShiftValid := slotShiftValid(index) probeWire.slots(index).decodeResultIsCrossReadOrWrite := decodeResult(Decoder.crossRead) || decodeResult(Decoder.crossWrite) probeWire.slots(index).decodeResultIsScheduler := decodeResult(Decoder.scheduler) @@ -873,11 +841,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ // It’s been a long time since I selected it. Need pipe val queueBeforeMaskWrite: Queue[VRFWriteRequest] = Module(new Queue(chiselTypeOf(maskedWriteUnit.enqueue.bits), entries = 1, pipe = true)) - dataInPipeQueue := Mux( - queueBeforeMaskWrite.io.deq.valid, - indexToOH(queueBeforeMaskWrite.io.deq.bits.instructionIndex, parameter.chainingSize), - 0.U - ) val writeSelect: UInt = Wire(UInt((parameter.chainingSize + 3).W)) val writeCavitation: UInt = VecInit(allVrfWriteAfterCheck.map(_.mask === 0.U)).asUInt @@ -919,25 +882,6 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ vrf.readCheck.zip(readCheckRequestVec).foreach{case (sink, source) => sink := source} readCheckResult.zip(vrf.readCheckResult).foreach{case (sink, source) => sink := source} - dataInAfterCheck := allVrfWriteAfterCheck.zipWithIndex.map { case (req, i) => - val check = vrf.writeAllow(i) - val enqReady = check && (!afterCheckValid(i) || afterCheckDequeueReady(i)) - val enqFire = enqReady && allVrfWrite(i).valid - allVrfWrite(i).ready := enqReady - when(enqFire) { - req := allVrfWrite(i).bits - } - val deqFire = afterCheckDequeueFire(i) - when(deqFire ^ enqFire) { - afterCheckValid(i) := enqFire - } - Mux( - afterCheckValid(i), - indexToOH(req.instructionIndex, parameter.chainingSize), - 0.U - ) - }.reduce(_ | _) - // Arbiter writeSelect := ffo(VecInit(afterCheckValid).asUInt & (~writeCavitation).asUInt) afterCheckDequeueReady.zipWithIndex.foreach { case (p, i) => @@ -1099,7 +1043,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ slotControl(slotIndex) := entranceControl maskGroupCountVec(slotIndex) := 0.U(parameter.maskGroupSizeBits.W) maskIndexVec(slotIndex) := 0.U(log2Ceil(parameter.maskGroupWidth).W) - pipeFinishVec(slotIndex) := false.B + slotOccupied(slotIndex) := true.B } enqueueFire } else { @@ -1110,18 +1054,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ slotControl(slotIndex) := slotControl(slotIndex + 1) maskGroupCountVec(slotIndex) := maskGroupCountVec(slotIndex + 1) maskIndexVec(slotIndex) := maskIndexVec(slotIndex + 1) - pipeFinishVec(slotIndex) := pipeFinishVec(slotIndex + 1) + slotOccupied(slotIndex) := slotOccupied(slotIndex + 1) } enqueueFire } } - val slotDequeueFire: Seq[Bool] = (slotCanShift.head && slotOccupied.head) +: slotEnqueueFire - Seq.tabulate(parameter.chainingSize) { slotIndex => - when(slotEnqueueFire(slotIndex) ^ slotDequeueFire(slotIndex)) { - slotOccupied(slotIndex) := slotEnqueueFire(slotIndex) - } - } slot0EnqueueFire := slotEnqueueFire.head // handshake @@ -1148,10 +1086,12 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ vrf.instructionWriteReport.bits.st := laneRequest.bits.store vrf.instructionWriteReport.bits.crossWrite := laneRequest.bits.decodeResult(Decoder.crossWrite) vrf.instructionWriteReport.bits.crossRead := laneRequest.bits.decodeResult(Decoder.crossRead) - vrf.instructionWriteReport.bits.stFinish := false.B - vrf.instructionWriteReport.bits.wWriteQueueClear := false.B - vrf.instructionWriteReport.bits.wBusClear := false.B - vrf.instructionWriteReport.bits.wQueueClear := false.B + // init state + vrf.instructionWriteReport.bits.state.stFinish := !laneRequest.bits.loadStore + // load need wait for write queue clear in lsu write queue + vrf.instructionWriteReport.bits.state.wWriteQueueClear := !(laneRequest.bits.loadStore && !laneRequest.bits.store) + vrf.instructionWriteReport.bits.state.wLaneLastReport := !laneRequest.valid + vrf.instructionWriteReport.bits.state.wLaneClear := false.B val elementSizeForOneRegister: Int = parameter.vLen / parameter.datapathWidth / parameter.laneNumber val nrMask: UInt = VecInit(Seq.tabulate(8){ i => @@ -1188,27 +1128,31 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ vrf.instructionWriteReport.bits.elementMask := shifterMask // clear record by instructionFinished - vrf.instructionLastReport := lsuLastReport | (instructionFinished & instructionUnrelatedMaskUnitVec.reduce(_ | _)) + vrf.instructionLastReport := instructionFinished + vrf.lsuLastReport := lsuLastReport vrf.lsuMaskGroupChange := lsuMaskGroupChange vrf.loadDataInLSUWriteQueue := loadDataInLSUWriteQueue - vrf.dataInCrossBus := dataInCrossBus - vrf.dataInWriteQueue := - crossLaneWriteQueue.map(q => Mux(q.io.deq.valid, indexToOH(q.io.deq.bits.instructionIndex, parameter.chainingSize), 0.U)).reduce(_ | _)| - Mux(topWriteQueue.valid, indexToOH(topWriteQueue.bits.instructionIndex, parameter.chainingSize), 0.U) | - maskedWriteUnit.maskedWrite1H | dataInPipeQueue | dataInAfterCheck - instructionFinished := instructionFinishedVec.reduce(_ | _) - crossWriteDataInSlot := crossWriteDataInSlotVec.reduce(_ | _) | dataInPipeQueue | - maskedWriteUnit.maskedWrite1H | dataInAfterCheck + vrf.dataInLane := instructionValid + instructionFinished := (~instructionValid).asUInt & instructionValidNext writeReadyForLsu := vrf.writeReadyForLsu vrfReadyToStore := vrf.vrfReadyToStore tokenManager.crossWriteReports.zipWithIndex.foreach {case (rpt, rptIndex) => rpt.valid := afterCheckDequeueFire(parameter.chainingSize + 1 + rptIndex) rpt.bits := allVrfWriteAfterCheck(parameter.chainingSize + 1 + rptIndex).instructionIndex } + // todo: add mask unit write token tokenManager.responseReport.valid := laneResponse.valid tokenManager.responseReport.bits := laneResponse.bits.instructionIndex tokenManager.responseFeedbackReport.valid := laneResponseFeedback.valid tokenManager.responseFeedbackReport.bits := laneResponseFeedback.bits.instructionIndex + val instInSlot: UInt = slotControl.zip(slotOccupied).map { case (slotState, occupied) => + Mux( + occupied, + indexToOH(slotState.laneRequest.instructionIndex, parameter.chainingSize), + 0.U + ) + }.reduce(_ | _) + instructionValid := tokenManager.instructionValid | instInSlot // slot write tokenManager.slotWriteReport.zipWithIndex.foreach {case (rpt, rptIndex) => diff --git a/t1/src/T1.scala b/t1/src/T1.scala index 83f17af72a..9f2ef3d1f6 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -451,7 +451,6 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa * - vd is v0 */ val specialInstruction: Bool = decodeResult(Decoder.special) || requestReg.bits.vdIsV0 - val dataInCrossBus = Wire(UInt(parameter.chainingSize.W)) val writeQueueClearVec = Wire(Vec(parameter.laneNumber, Bool())) val writeQueueClear: Bool = !writeQueueClearVec.asUInt.orR @@ -571,7 +570,6 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa * this signal is used to update the `control.endTag`. */ val lsuFinished: Bool = ohCheck(lsu.lastReport, control.record.instructionIndex, parameter.chainingSize) - val busClear: Bool = !ohCheck(dataInCrossBus, control.record.instructionIndex, parameter.chainingSize) // instruction is allocated to this slot. when(instructionToSlotOH(index)) { // instruction metadata @@ -579,8 +577,6 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa // TODO: remove control.record.isLoadStore := isLoadStoreType control.record.maskType := maskType - control.record.needWaitWriteQueueClear := - requestReg.bits.decodeResult(Decoder.crossWrite) || requestReg.bits.decodeResult(Decoder.maskUnit) // control signals control.state.idle := false.B control.state.wLast := false.B @@ -593,7 +589,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa // state machine starts here .otherwise { when(laneAndLSUFinish) { - control.state.wLast := !control.record.needWaitWriteQueueClear || (busClear && writeQueueClear) + control.state.wLast := true.B } // TODO: execute first, then commit when(responseCounter === control.record.instructionIndex && response.fire) { @@ -1500,7 +1496,6 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa lane.lsuMaskGroupChange := lsu.lsuMaskGroupChange lane.loadDataInLSUWriteQueue := lsu.dataInWriteQueue(index) - lane.dataInCrossBus := dataInCrossBus // 2 + 3 = 5 val rowWith: Int = log2Ceil(parameter.datapathWidth / 8) + log2Ceil(parameter.laneNumber) lane.writeCount := @@ -1551,8 +1546,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa lsu.vrfReadyToStore := VecInit(laneVec.map(_.vrfReadyToStore)).asUInt.andR // 连lane的环 - dataInCrossBus := parameter.crossLaneConnectCycles.zipWithIndex.map { case (cycles, index) => - cycles.zipWithIndex.map { case (cycle, portIndex) => + parameter.crossLaneConnectCycles.zipWithIndex.foreach { case (cycles, index) => + cycles.zipWithIndex.foreach { case (cycle, portIndex) => // read source <=> write sink val readSourceIndex = (2 * index + portIndex) % parameter.laneNumber val readSourcePort = (2 * index + portIndex) / parameter.laneNumber @@ -1574,10 +1569,10 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa 0.U.asTypeOf(new EmptyBundle), cycle ).valid - connectWithShifter(cycle, id = Some((a: WriteBusData) => a.instructionIndex))(laneVec(index).writeBusPort(portIndex).deq, - laneVec(readSourceIndex).writeBusPort(readSourcePort).enq).get | laneVec(index).crossWriteDataInSlot - }.reduce(_ | _) - }.reduce(_ | _) + connectWithShifter(cycle)(laneVec(index).writeBusPort(portIndex).deq, + laneVec(readSourceIndex).writeBusPort(readSourcePort).enq).get + } + } memoryPorts.zip(lsu.tlPort).foreach { case (source, sink) => diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala index dface7ea92..b7778dfc78 100644 --- a/t1/src/vrf/VRF.scala +++ b/t1/src/vrf/VRF.scala @@ -195,12 +195,11 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar @public val instructionLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W))) - /** data in write queue */ @public - val dataInWriteQueue: UInt = IO(Input(UInt(parameter.chainingSize.W))) + val lsuLastReport: UInt = IO(Input(UInt(parameter.chainingSize.W))) @public - val dataInCrossBus: UInt = IO(Input(UInt(parameter.chainingSize.W))) + val dataInLane: UInt = IO(Input(UInt(parameter.chainingSize.W))) @public val lsuMaskGroupChange: UInt = IO(Input(UInt(parameter.chainingSize.W))) @@ -452,7 +451,6 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar loadUnitReadPorts.map(p => UIntToOH((p.bits.vs ## p.bits.offset)(parameter.vrfOffsetBits + 3 - 1, 0))) Seq(chainingRecord, chainingRecordCopy).foreach{ recordVec => recordVec.zipWithIndex.foreach { case (record, i) => - val dataIndexWriteQueue = ohCheck(dataInWriteQueue, record.bits.instIndex, parameter.chainingSize) val dataInLsuQueue = ohCheck(loadDataInLSUWriteQueue, record.bits.instIndex, parameter.chainingSize) // elementMask update by write val writeUpdateValidVec: Seq[Bool] = writePort.map( p => @@ -467,32 +465,33 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar // all elementMask update val elementUpdateValid: Bool = (writeUpdateValidVec ++ loadUpdateValidVec).reduce(_ || _) val elementUpdate1H: UInt = (writeUpdate1HVec ++ loadUpdate1HVec).reduce(_ | _) - val queueClear = !dataIndexWriteQueue - val dataInBusCheck = ohCheck(dataInCrossBus, record.bits.instIndex, parameter.chainingSize) - val busClear = !dataInBusCheck || !record.bits.crossWrite - when(ohCheck(instructionLastReport, record.bits.instIndex, parameter.chainingSize)) { - when(record.bits.ls) { - record.bits.stFinish := true.B - }.otherwise { - record.bits.wWriteQueueClear := true.B - } + val dataInLaneCheck = ohCheck(dataInLane, record.bits.instIndex, parameter.chainingSize) + val laneLastReport = ohCheck(instructionLastReport, record.bits.instIndex, parameter.chainingSize) + val lsuFinish = ohCheck(lsuLastReport, record.bits.instIndex, parameter.chainingSize) + // only wait lane clear + val waitLaneClear = record.bits.state.stFinish && record.bits.state.wWriteQueueClear && record.bits.state.wLaneLastReport + val stateClear: Bool = waitLaneClear && record.bits.state.wLaneClear + + when(lsuFinish) { + record.bits.state.stFinish := true.B } - when(record.bits.stFinish && (!dataInLsuQueue || record.bits.st) && record.valid) { - when(!dataIndexWriteQueue) { - record.valid := false.B - } + + when(laneLastReport) { + record.bits.state.wLaneLastReport := true.B + } + + when(record.bits.state.stFinish && !dataInLsuQueue) { + record.bits.state.wWriteQueueClear := true.B } - when(record.bits.wWriteQueueClear) { - when(busClear) { - record.bits.wBusClear := true.B - } - when((busClear || record.bits.wBusClear) && queueClear) { - record.bits.wQueueClear := true.B - } + + when(waitLaneClear && !dataInLaneCheck) { + record.bits.state.wLaneClear := true.B } - when(record.bits.wWriteQueueClear && record.bits.wBusClear && record.bits.wQueueClear) { - record.valid := false.B + + when(stateClear) { + record.valid := true.B } + when(recordEnq(i)) { record := initRecord }.elsewhen(elementUpdateValid) {