diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
index d9b637925..08b3512c5 100644
--- a/t1/src/Lane.scala
+++ b/t1/src/Lane.scala
@@ -7,7 +7,7 @@ import chisel3._
 import chisel3.experimental.hierarchy.{Definition, Instance, Instantiate, instantiable, public}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.probe.{Probe, ProbeValue, define}
-import chisel3.properties.{Class, ClassType, Path, Property}
+import chisel3.properties.{AnyClassType, Class, ClassType, Path, Property}
 import chisel3.util._
 import chisel3.util.experimental.decode.DecodeBundle
 import org.chipsalliance.t1.rtl.decoder.Decoder
@@ -16,11 +16,10 @@ import org.chipsalliance.t1.rtl.vrf.{RamType, VRF, VRFParam, VRFProbe}
 
 @instantiable
 class LaneOM extends Class {
-  val vfuOMType: ClassType = Definition(new VFUOM).getClassType
   @public
-  val vfus = IO(Output(Property[Seq[vfuOMType.Type]]()))
+  val vfus = IO(Output(Property[Seq[AnyClassType]]()))
   @public
-  val vfusIn = IO(Input(Property[Seq[vfuOMType.Type]]()))
+  val vfusIn = IO(Input(Property[Seq[AnyClassType]]()))
   vfus := vfusIn
 }
 
@@ -823,7 +822,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     executeOccupied,
     VFUNotClear
   )
-  omInstance.vfusIn := Property(vfus.map(_.om.as(Definition(new VFUOM).getClassType)))
+  omInstance.vfusIn := Property(vfus.map(_.om.asAnyClassType))
 
   // It’s been a long time since I selected it. Need pipe
   val queueBeforeMaskWrite: Queue[VRFWriteRequest] =
diff --git a/t1/src/T1.scala b/t1/src/T1.scala
index 19bc33fdc..2d29ea78c 100644
--- a/t1/src/T1.scala
+++ b/t1/src/T1.scala
@@ -10,7 +10,7 @@ import chisel3.util._
 import chisel3.util.experimental.decode._
 import tilelink.{TLBundle, TLBundleParameter, TLChannelAParameter, TLChannelDParameter}
 import chisel3.probe.{Probe, ProbeValue, define, force}
-import chisel3.properties.{Class, ClassType, Property}
+import chisel3.properties.{AnyClassType, Class, ClassType, Property}
 import chisel3.util.experimental.BitSet
 import org.chipsalliance.t1.rtl.decoder.Decoder
 import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
@@ -22,11 +22,10 @@ import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe}
 //       3. Lane(Retime, VRF memory type, id, multiple instances(does it affect dedup? not for sure))
 @instantiable
 class T1OM extends Class {
-  val laneOMType: ClassType = Definition(new LaneOM).getClassType
   @public
-  val lanes = IO(Output(Property[Seq[laneOMType.Type]]()))
+  val lanes = IO(Output(Property[Seq[AnyClassType]]()))
   @public
-  val lanesIn = IO(Input(Property[Seq[laneOMType.Type]]()))
+  val lanesIn = IO(Input(Property[Seq[AnyClassType]]()))
   lanes := lanesIn
 }
 
@@ -1509,7 +1508,7 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
     lane
   }
 
-  omInstance.lanesIn := Property(laneVec.map(_.om.as(Definition(new LaneOM).getClassType)))
+  omInstance.lanesIn := Property(laneVec.map(_.om.asAnyClassType))
 
   define(lsuProbe, lsu.probe)