diff --git a/t1/src/mask/MaskCompress.scala b/t1/src/mask/MaskCompress.scala
index cc8429580..24f597259 100644
--- a/t1/src/mask/MaskCompress.scala
+++ b/t1/src/mask/MaskCompress.scala
@@ -41,6 +41,7 @@ class MaskCompress(parameter: T1Parameter) extends Module {
   val viota    = in.bits.uop === "b000".U
   val mv       = in.bits.uop === "b010".U
   val mvRd     = in.bits.uop === "b011".U
+  val writeRD  = in.bits.uop === BitPat("b?11")
   val ffoType  = in.bits.uop === BitPat("b11?")
 
   val eew1H:           UInt      = UIntToOH(in.bits.eew)(2, 0)
@@ -196,7 +197,7 @@ class MaskCompress(parameter: T1Parameter) extends Module {
   )
 
   // todo
-  out.compressValid := (compressTailValid || (compressDeqValid && in.fire)) && !mvRd
+  out.compressValid := (compressTailValid || (compressDeqValid && in.fire)) && !writeRD
   out.groupCounter  := Mux(compress, compressWriteGroupCount, in.bits.groupCounter)
 
   when(newInstruction && ffoInstruction) {