From 13b2b1686a8d0f440c3e7a71fa7391c619a9e7a4 Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Thu, 21 Nov 2024 11:01:22 +0800 Subject: [PATCH] [rtl] fix source with for load unit source queue. --- t1/src/lsu/LSU.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index e8ab41e00..7c93e09ed 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -329,7 +329,7 @@ class LSU(param: LSUParameter) extends Module { p := VecInit(queueCount.map(_ =/= 0.U)).asUInt | dataInMSHR } - val sourceQueue = Queue.io(UInt(param.mshrParam.sourceWidth.W), param.sourceQueueSize) + val sourceQueue = Queue.io(UInt(param.mshrParam.cacheLineIndexBits.W), param.sourceQueueSize) // load unit connect axi4Port.ar.valid := loadUnit.memRequest.valid && sourceQueue.enq.ready axi4Port.ar.bits <> DontCare