[rtl] fix source with for load unit source queue.

chipsalliance · Nov 21, 2024 · 13b2b16 · 13b2b16
1 parent a5df36a
commit 13b2b16
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -329,7 +329,7 @@ class LSU(param: LSUParameter) extends Module {
     p := VecInit(queueCount.map(_ =/= 0.U)).asUInt | dataInMSHR
   }
 
-  val sourceQueue = Queue.io(UInt(param.mshrParam.sourceWidth.W), param.sourceQueueSize)
+  val sourceQueue = Queue.io(UInt(param.mshrParam.cacheLineIndexBits.W), param.sourceQueueSize)
   // load unit connect
   axi4Port.ar.valid         := loadUnit.memRequest.valid && sourceQueue.enq.ready
   axi4Port.ar.bits <> DontCare