diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala index d7d739929..505b57be6 100644 --- a/rocketv/src/RocketCore.scala +++ b/rocketv/src/RocketCore.scala @@ -51,6 +51,10 @@ class RocketProbe(param: RocketParameter) extends Bundle { val idle: Bool = Bool() // fpu score board val fpuScoreboard: Option[FPUScoreboardProbe] = Option.when(param.usingFPU)(new FPUScoreboardProbe) + + val wbRegPc: UInt = UInt(param.iBufParameter.vaddrBitsExtended.W) + val t1IssueEnq: Option[DecoupledIO[T1Issue]] = + Option.when(param.usingT1)(DecoupledIO(new T1Issue(param.xLen, param.vLen))) } object RocketParameter { @@ -1634,6 +1638,11 @@ class Rocket(val parameter: RocketParameter) probeWire.isVectorWrite := t1RetireQueue.map(q => q.io.deq.fire).getOrElse(false.B) probeWire.idle := vectorEmpty + probeWire.wbRegPc := wbRegPc + probeWire.t1IssueEnq.foreach { case t1IssueEnq => + t1IssueEnq := t1IssueQueue.io.enq + } + probeWire.fpuScoreboard.foreach { case fpProbe => fpProbe.memSetScoreBoard := wbValid && wbDcacheMiss && wbRegDecodeOutput(parameter.decoderParameter.wfd) fpProbe.vectorSetScoreBoard := wbValid && wbRegDecodeOutput(parameter.decoderParameter.wfd) && Option diff --git a/t1/src/T1.scala b/t1/src/T1.scala index b87b3d043..6a78a2b7c 100644 --- a/t1/src/T1.scala +++ b/t1/src/T1.scala @@ -325,23 +325,26 @@ case class T1Parameter( } class T1Probe(parameter: T1Parameter) extends Bundle { - val instructionCounter: UInt = UInt(parameter.instructionIndexBits.W) - val instructionIssue: Bool = Bool() - val issueTag: UInt = UInt(parameter.instructionIndexBits.W) - val retireValid: Bool = Bool() + val instructionCounter: UInt = UInt(parameter.instructionIndexBits.W) + val instructionIssue: Bool = Bool() + val issueTag: UInt = UInt(parameter.instructionIndexBits.W) + val retireValid: Bool = Bool() + // for profiler + val requestReg: ValidIO[InstructionPipeBundle] = ValidIO(new InstructionPipeBundle(parameter)) + val requestRegReady: Bool = Bool() // write queue enq for mask unit - val writeQueueEnq: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W)) - val writeQueueEnqMask: UInt = UInt((parameter.datapathWidth / 8).W) + val writeQueueEnq: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W)) + val writeQueueEnqMask: UInt = UInt((parameter.datapathWidth / 8).W) // mask unit instruction valid - val instructionValid: UInt = UInt((parameter.chainingSize * 2).W) + val instructionValid: UInt = UInt((parameter.chainingSize * 2).W) // instruction index for check rd - val responseCounter: UInt = UInt(parameter.instructionIndexBits.W) + val responseCounter: UInt = UInt(parameter.instructionIndexBits.W) // probes - val lsuProbe: LSUProbe = new LSUProbe(parameter.lsuParameters) - val laneProbes: Vec[LaneProbe] = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam)) - val issue: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W)) - val retire: ValidIO[UInt] = Valid(UInt(parameter.xLen.W)) - val idle: Bool = Bool() + val lsuProbe: LSUProbe = new LSUProbe(parameter.lsuParameters) + val laneProbes: Vec[LaneProbe] = Vec(parameter.laneNumber, new LaneProbe(parameter.laneParam)) + val issue: ValidIO[UInt] = Valid(UInt(parameter.instructionIndexBits.W)) + val retire: ValidIO[UInt] = Valid(UInt(parameter.xLen.W)) + val idle: Bool = Bool() } class T1Interface(parameter: T1Parameter) extends Record { @@ -1778,6 +1781,8 @@ class T1(val parameter: T1Parameter) probeWire.instructionIssue := requestRegDequeue.fire probeWire.issueTag := requestReg.bits.instructionIndex probeWire.retireValid := retire + probeWire.requestReg := requestReg + probeWire.requestRegReady := requestRegDequeue.ready // maskUnitWrite maskUnitWriteReady probeWire.writeQueueEnq.valid := maskUnitWrite.valid && maskUnitWriteReady probeWire.writeQueueEnq.bits := maskUnitWrite.bits.instructionIndex diff --git a/t1rocket/src/T1RocketTile.scala b/t1rocket/src/T1RocketTile.scala index 8b2fbc520..222289819 100644 --- a/t1rocket/src/T1RocketTile.scala +++ b/t1rocket/src/T1RocketTile.scala @@ -31,6 +31,9 @@ import org.chipsalliance.rvdecoderdb.Instruction import org.chipsalliance.t1.rtl.vrf.RamType import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw} import org.chipsalliance.t1.rtl.{T1, T1Parameter, T1Probe, VFUInstantiateParameter} +import chisel3.util.DecoupledIO +import org.chipsalliance.t1.rtl.T1Issue +import org.chipsalliance.rocketv.T1Retire object T1RocketTileParameter { implicit def bitSetP: upickle.default.ReadWriter[BitSet] = upickle.default @@ -405,6 +408,9 @@ class T1RocketProbe(parameter: T1RocketTileParameter) extends Bundle { val rocketProbe: RocketProbe = Output(new RocketProbe(parameter.rocketParameter)) val fpuProbe: Option[FPUProbe] = parameter.fpuParameter.map(param => Output(new FPUProbe(param))) val t1Probe: T1Probe = Output(new T1Probe(parameter.t1Parameter)) + + val t1IssueDeq: DecoupledIO[T1Issue] = DecoupledIO(new T1Issue(parameter.xLen, parameter.vLen)) + val t1Retire: T1Retire = Output(new T1Retire(parameter.xLen)) } class T1RocketTileInterface(parameter: T1RocketTileParameter) extends Bundle { @@ -555,5 +561,8 @@ class T1RocketTile(val parameter: T1RocketTileParameter) probeWire.fpuProbe.foreach { fpuProbe => fpuProbe := probe.read(fpu.get.io.fpuProbe) } + + probeWire.t1IssueDeq := t1.io.issue + probeWire.t1Retire := t1.io.retire } } diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala index 35adc1911..b9a208bac 100644 --- a/t1rocketemu/src/TestBench.scala +++ b/t1rocketemu/src/TestBench.scala @@ -14,6 +14,8 @@ import chisel3.util.{HasExtModuleInline, PopCount, UIntToOH, Valid} import org.chipsalliance.amba.axi4.bundle._ import org.chipsalliance.t1.t1rocketemu.dpi._ import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter} +import org.chipsalliance.t1.rtl.T1Probe +import org.chipsalliance.t1.tile.T1RocketProbe @instantiable class TestBenchOM extends Class { @@ -353,4 +355,28 @@ class TestBench(val parameter: T1RocketTileParameter) when(quitFlag && t1Probe.idle && rocketProbe.idle) { stop(cf"""{"event":"SimulationEnd", "cycle":${simulationTime}}\n""") } + + // t1rocket ProfData + layer.block(layers.Verification) { + val profData = Module(new Module { + override def desiredName: String = "ProfData" + val probe = IO(Input(new T1RocketProbe(parameter))) + + val t1IssueEnqPc = WireInit(probe.rocketProbe.wbRegPc) + val t1IssueEnq = WireInit(probe.rocketProbe.t1IssueEnq.get) + val t1IssueDeq = WireInit(probe.t1IssueDeq) + val t1IssueRegDeq = WireInit(probe.t1Probe.requestReg) + val t1IssueRegDeqReady = WireInit(probe.t1Probe.requestRegReady) + val t1Retire = WireInit(probe.t1Retire) + + dontTouch(this.clock) + dontTouch(this.reset) + dontTouch(t1IssueEnq) + dontTouch(t1IssueDeq) + dontTouch(t1IssueRegDeq) + dontTouch(t1IssueRegDeqReady) + dontTouch(t1Retire) + }) + profData.probe := t1RocketProbe + } }