diff --git a/subsystem/src/LazyT1.scala b/subsystem/src/LazyT1.scala
index e4f635e932..b963789e70 100644
--- a/subsystem/src/LazyT1.scala
+++ b/subsystem/src/LazyT1.scala
@@ -4,6 +4,7 @@
 package org.chipsalliance.t1.subsystem
 
 import chisel3._
+import chisel3.util.experimental.BoringUtils.bore
 import chisel3.experimental.SerializableModuleGenerator
 import chisel3.properties.{ClassType, Path, Property}
 import freechips.rocketchip.diplomacy.AddressSet
@@ -11,6 +12,7 @@ import freechips.rocketchip.subsystem.{BaseSubsystem, InstantiatesHierarchicalEl
 import org.chipsalliance.cde.config._
 import org.chipsalliance.t1.rockettile.{AbstractLazyT1, AbstractLazyT1ModuleImp, T1LSUParameter}
 import org.chipsalliance.t1.rtl.{T1, T1Parameter}
+import org.chipsalliance.t1.rtl.lsu.LSUProbe
 
 case object T1Generator extends Field[SerializableModuleGenerator[T1, T1Parameter]]
 
@@ -32,6 +34,37 @@ class LazyT1Imp(outer: LazyT1)(implicit p: Parameters) extends AbstractLazyT1Mod
   // We insist using the json config for Vector for uArch tuning.
   val t1: T1 = Module(outer.generator.module())
 
+  // Since T1 doesn't split the interface and implementations into two packages.
+  // we should consider doing this in the future. But now we just instantiate Xizhimen here.
+  // this remind me that, for all Modules, being a FixedIOModule is really important.
+  // that makes us being able to split def/impl easily.
+  // In the future plan, we will pull Xizhimen up to RenMinGuangChang which will also include Monitor modules from Scalar.
+
+  // Monitor
+  val lsuProbe = probe.read(t1.lsuProbe).suggestName("lsuProbe")
+  val laneProbes = t1.laneProbes.zipWithIndex.map{case (p, idx) =>
+    val wire = Wire(p.cloneType)
+    wire := probe.read(p)
+    wire
+  }
+  val laneVrfProbes = t1.laneVrfProbes.zipWithIndex.map{case (p, idx) =>
+    val wire = Wire(p.cloneType).suggestName(s"lane${idx}VrfProbe")
+    wire := probe.read(p)
+    wire
+  }
+
+  // TODO: gather XiZhiMen into a module, making XiZhiMen into an interface package.
+  withClockAndReset(clock, reset)(Module(new Module {
+    // h/t: GrandCentral
+    override def desiredName: String = "XiZhiMen"
+    val lsuProbeMonitor: LSUProbe = bore(lsuProbe)
+    dontTouch(lsuProbeMonitor)
+    val laneProbesMonitor = laneProbes.map(bore(_))
+    laneProbesMonitor.foreach(dontTouch(_))
+    val laneVrfProbesMonitor = laneVrfProbes.map(bore(_))
+    laneVrfProbesMonitor.foreach(dontTouch(_))
+  }))
+
   t1.request.valid := request.valid
   t1.request.bits.instruction := request.bits.instruction
   t1.request.bits.src1Data := request.bits.rs1Data