diff --git a/t1/src/decoder/attribute/fmaUOP.scala b/t1/src/decoder/attribute/fmaUOP.scala new file mode 100644 index 000000000..8cbbaad69 --- /dev/null +++ b/t1/src/decoder/attribute/fmaUOP.scala @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileCopyrightText: 2022 Jiuyang Liu + +package org.chipsalliance.t1.rtl.decoder.attribute + +import org.chipsalliance.t1.rtl.decoder.T1DecodePattern + +trait FMAUopType extends Uop +object FMAT0 extends FMAUopType +object FMAT1 extends FMAUopType +object FMAT2 extends FMAUopType +object FMAT3 extends FMAUopType +object FMAT4 extends FMAUopType +object FMAT5 extends FMAUopType +object FMAT6 extends FMAUopType +object FMAT7 extends FMAUopType +object FMAT8 extends FMAUopType +object FMADC extends FMAUopType + +object fmaUOP { + def apply(t1DecodePattern: T1DecodePattern): fmaUOP = { + Seq( + t0 _ -> FMAT0, + t1 _ -> FMAT1, + t2 _ -> FMAT2, + t3 _ -> FMAT3, + t4 _ -> FMAT4, + t5 _ -> FMAT5, + t6 _ -> FMAT6, + t7 _ -> FMAT7, + t8 _ -> FMAT8, + dc _ -> FMADC, + ).collectFirst { + case (fn, tpe) if fn(t1DecodePattern) => fmaUOP(tpe) + }.get + + } + def t0(t1DecodePattern: T1DecodePattern): Boolean = { + val allMatched: Seq[String] = Seq( + "vfadd", + "vfmacc", + "vfmul", + "vfredosum", + "vfredusum" + ) + allMatched.contains(t1DecodePattern.instruction.name) + } + def t1(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t2(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t3(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t4(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t5(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t6(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t7(t1DecodePattern: T1DecodePattern): Boolean = ??? + def t8(t1DecodePattern: T1DecodePattern): Boolean = ??? + def dc(t1DecodePattern: T1DecodePattern): Boolean = ??? +} + +case class fmaUOP(value: FMAUopType) extends UopDecodeAttribute[FMAUopType] { + override val description: String = "Some Thing" +} \ No newline at end of file