From 0ed15ef74d0752d9f1320b74bae4b4622907907f Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Mon, 23 Dec 2024 16:29:25 +0800 Subject: [PATCH] [rtl] add last report for empty instruction. --- t1/src/Lane.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala index 934e9af27..1c8893634 100644 --- a/t1/src/Lane.scala +++ b/t1/src/Lane.scala @@ -1183,12 +1183,16 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[ instructionFinishInSlot := (~instructionValid).asUInt & instructionValidNext + val emptyInstValid: Bool = RegNext(laneRequest.bits.issueInst && !vrf.instructionWriteReport.valid, false.B) + val emptyInstCount: UInt = RegNext(indexToOH(laneRequest.bits.instructionIndex, parameter.chainingSize)) + val emptyReport: UInt = maskAnd(emptyInstValid, emptyInstCount).asUInt + // clear record by instructionFinished vrf.instructionLastReport := instructionFinishInSlot vrf.lsuLastReport := lsuLastReport vrf.loadDataInLSUWriteQueue := loadDataInLSUWriteQueue vrf.dataInLane := instructionValid - instructionFinished := vrf.vrfSlotRelease + instructionFinished := vrf.vrfSlotRelease | emptyReport writeReadyForLsu := vrf.writeReadyForLsu vrfReadyToStore := vrf.vrfReadyToStore tokenManager.crossWriteReports.zipWithIndex.foreach { case (rpt, rptIndex) =>