From 0cd18e42f78fc86b0638df7f75ac8fa3f9b8fb0c Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Wed, 20 Nov 2024 17:54:55 +0800 Subject: [PATCH] [rtl] disable memory interleaving. --- t1/src/lsu/LSU.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala index 38d12a06a..15d366b89 100644 --- a/t1/src/lsu/LSU.scala +++ b/t1/src/lsu/LSU.scala @@ -210,8 +210,7 @@ class LSU(param: LSUParameter) extends Module { val useStoreUnit: Bool = alwaysMerge && request.bits.instructionInformation.isStore val useOtherUnit: Bool = !alwaysMerge val addressCheck: Bool = otherUnit.status.idle && (!useOtherUnit || (loadUnit.status.idle && storeUnit.status.idle)) - val unitReady: Bool = - (useLoadUnit && loadUnit.status.idle) || (useStoreUnit && storeUnit.status.idle) || (useOtherUnit && otherUnit.status.idle) + val unitReady: Bool = loadUnit.status.idle && storeUnit.status.idle && otherUnit.status.idle request.ready := unitReady && addressCheck val requestFire = request.fire val reqEnq: Vec[Bool] = VecInit(