From 0b535068593b9d385b12623b441762e4935bb562 Mon Sep 17 00:00:00 2001
From: qinjun-li <liqinjun1994@gmail.com>
Date: Tue, 20 Aug 2024 13:50:59 +0800
Subject: [PATCH] [rocketv] fix exRegRsMSB in bypass(todo).

---
 rocketv/src/RocketCore.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
index b55cd1a709..3cbbad64f9 100644
--- a/rocketv/src/RocketCore.scala
+++ b/rocketv/src/RocketCore.scala
@@ -786,9 +786,9 @@ class Rocket(val parameter: RocketParameter)
         val bypassSource = PriorityEncoder(idBypassSources(i))
         exRegRsBypass(i) := doBypass
         exRegRsLSB(i) := bypassSource
+        exRegRsMSB(i) := idRs(i) >> log2Ceil(bypassSources.size)
         when(idRen(i) && !doBypass) {
           exRegRsLSB(i) := idRs(i)(log2Ceil(bypassSources.size) - 1, 0)
-          exRegRsMSB(i) := idRs(i) >> log2Ceil(bypassSources.size)
         }
       }
       when(idIllegalInstruction || idVirtualInstruction) {