From 056a50ddf16442b2a1d35890d3b6ae91e1c5c44d Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Wed, 20 Nov 2024 20:56:27 +0800 Subject: [PATCH] [rtl] fix mask select in mask unit. --- t1/src/mask/MaskUnit.scala | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala index bb523f260..652b86e0b 100644 --- a/t1/src/mask/MaskUnit.scala +++ b/t1/src/mask/MaskUnit.scala @@ -434,7 +434,7 @@ class MaskUnit(parameter: T1Parameter) extends Module { val slideAddressGen: SlideIndexGen = Module(new SlideIndexGen(parameter)) slideAddressGen.newInstruction := instReq.valid & instReq.bits.vl.orR slideAddressGen.instructionReq := instReg - slideAddressGen.slideMaskInput := cutUInt(v0.asUInt, 8)(slideAddressGen.slideGroupOut) + slideAddressGen.slideMaskInput := cutUInt(v0.asUInt, parameter.laneNumber)(slideAddressGen.slideGroupOut) val firstRequest: Bool = RegInit(false.B) val viotaCounterAdd: Bool = Wire(Bool()) @@ -519,10 +519,7 @@ class MaskUnit(parameter: T1Parameter) extends Module { ) & Fill(parameter.laneNumber, validExecuteGroup) // handle mask - val readMaskSelect: UInt = - (executeGroup >> log2Ceil(parameter.datapathWidth / parameter.laneNumber)).asUInt - val readMaskInput: UInt = cutUInt(v0.asUInt, parameter.maskGroupWidth)(readMaskSelect) - val selectReadStageMask: UInt = cutUIntBySize(readMaskInput, 4)(executeGroup(1, 0)) + val selectReadStageMask: UInt = cutUInt(v0.asUInt, parameter.laneNumber)(executeGroup) val readMaskCorrection: UInt = Mux(instReg.maskType, selectReadStageMask, -1.S(parameter.laneNumber.W).asUInt) & vlBoundaryCorrection