diff --git a/ipemu/src/TestBench.scala b/ipemu/src/TestBench.scala
index 1570aadd1..068236a92 100644
--- a/ipemu/src/TestBench.scala
+++ b/ipemu/src/TestBench.scala
@@ -5,8 +5,9 @@ package org.chipsalliance.t1.ipemu
 
 import chisel3._
 import chisel3.experimental.SerializableModuleGenerator
-import chisel3.probe._
+import chisel3.experimental.dataview.DataViewable
 import chisel3.util.experimental.BoringUtils.bore
+import org.chipsalliance.amba.axi4.bundle._
 import org.chipsalliance.t1.ipemu.dpi._
 import org.chipsalliance.t1.rtl.{T1, T1Parameter}
 
@@ -135,36 +136,84 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
   peekIssue.ready.ref := dut.request.ready
   peekIssue.issueIdx.ref := t1Probe.instructionCounter
 
-  dut.memoryPorts.zipWithIndex.foreach {
-    case (bundle, idx) =>
-      val peek = Module(new PeekTL(dut.parameter.tlParam.bundle(), latPeekTL))
-      peek.clock.ref := clockGen.clock
-      peek.channel.ref := idx.U
-      peek.aBits_opcode.ref := bundle.a.bits.opcode
-      peek.aBits_param.ref := bundle.a.bits.param
-      peek.aBits_size.ref := bundle.a.bits.size
-      peek.aBits_source.ref := bundle.a.bits.source
-      peek.aBits_address.ref := bundle.a.bits.address
-      peek.aBits_mask.ref := bundle.a.bits.mask
-      peek.aBits_data.ref := bundle.a.bits.data
-      peek.aBits_corrupt.ref := bundle.a.bits.corrupt
-
-      peek.aValid.ref := bundle.a.valid
-      peek.dReady.ref := bundle.d.ready
-
-      val poke = Module(new PokeTL(dut.parameter.tlParam.bundle(), latPokeTL))
-      poke.clock.ref := clockGen.clock
-      poke.channel.ref := idx.U
-      bundle.d.bits.opcode := poke.dBits_opcode.ref
-      bundle.d.bits.param := poke.dBits_param.ref
-      bundle.d.bits.sink := poke.dBits_sink.ref
-      bundle.d.bits.source := poke.dBits_source.ref
-      bundle.d.bits.size := poke.dBits_size.ref
-      bundle.d.bits.denied := poke.dBits_denied.ref
-      bundle.d.bits.data := poke.dBits_data.ref
-      bundle.d.bits.corrupt := poke.dBits_corrupt.ref
-      bundle.d.valid := poke.dValid.ref
-      poke.dReady.ref := bundle.d.ready
-      bundle.a.ready := poke.aReady.ref
+  Seq(
+    dut.highBandwidthLoadStorePort,
+    dut.indexedLoadStorePort
+  ).map(_.viewAs[AXI4RWIrrevocableVerilog]).zip(
+    Seq("highBandwidthPort", "indexedAccessPort")
+  ).foreach {
+    case (bundle: AXI4RWIrrevocableVerilog, channelName: String) =>
+      val aw = Module(new awDpi(channelName, chiselTypeOf(bundle), latPeekTL)).suggestName(s"${channelName}_aw_dpi")
+      val w = Module(new wDpi(channelName, chiselTypeOf(bundle), latPeekTL)).suggestName(s"${channelName}_w_dpi")
+      val b = Module(new bDpi(channelName, chiselTypeOf(bundle), latPeekTL)).suggestName(s"${channelName}_b_dpi")
+      val ar = Module(new arDpi(channelName, chiselTypeOf(bundle), latPeekTL)).suggestName(s"${channelName}_ar_dpi")
+      val r = Module(new rDpi(channelName, chiselTypeOf(bundle), latPeekTL)).suggestName(s"${channelName}_r_dpi")
+
+
+
+      aw.clock.ref := clock.asBool
+      w.clock.ref := clock.asBool
+      b.clock.ref := clock.asBool
+      ar.clock.ref := clock.asBool
+      r.clock.ref := clock.asBool
+      // IP -> Sim
+      aw.AWID.ref := bundle.AWID
+      aw.AWADDR.ref := bundle.AWADDR
+      aw.AWLEN.ref := bundle.AWLEN
+      aw.AWSIZE.ref := bundle.AWSIZE
+      aw.AWBURST.ref := bundle.AWBURST
+      aw.AWLOCK.ref := bundle.AWLOCK
+      aw.AWCACHE.ref := bundle.AWCACHE
+      aw.AWPROT.ref := bundle.AWPROT
+      aw.AWQOS.ref := bundle.AWQOS
+      aw.AWREGION.ref := bundle.AWREGION
+      aw.AWUSER.ref := bundle.AWUSER
+      aw.AWVALID.ref := bundle.AWVALID
+      // Sim -> IP
+      bundle.AWREADY := aw.AWVALID.ref
+
+      // IP -> Sim
+      w.WDATA.ref := bundle.WDATA
+      w.WSTRB.ref := bundle.WSTRB
+      w.WLAST.ref := bundle.WLAST
+      w.WUSER.ref := bundle.WUSER
+      w.WVALID.ref := bundle.WVALID
+      // Sim -> IP
+      bundle.WREADY := w.WREADY.ref
+
+      // Sim -> IP
+      bundle.BID := b.BID.ref
+      bundle.BRESP := b.BRESP.ref
+      bundle.BUSER := b.BUSER.ref
+      bundle.BVALID := b.BVALID.ref
+
+      // IP -> Sim
+      b.BREADY.ref := bundle.BREADY
+
+      // IP -> Sim
+      ar.ARID.ref := bundle.ARID
+      ar.ARADDR.ref := bundle.ARADDR
+      ar.ARLEN.ref := bundle.ARLEN
+      ar.ARSIZE.ref := bundle.ARSIZE
+      ar.ARBURST.ref := bundle.ARBURST
+      ar.ARLOCK.ref := bundle.ARLOCK
+      ar.ARCACHE.ref := bundle.ARCACHE
+      ar.ARPROT.ref := bundle.ARPROT
+      ar.ARQOS.ref := bundle.ARQOS
+      ar.ARREGION.ref := bundle.ARREGION
+      ar.ARUSER.ref := bundle.ARUSER
+      ar.ARVALID.ref := bundle.ARVALID
+      // IP -> Sim
+      bundle.ARREADY := ar.ARREADY.ref
+
+      // Sim -> IP
+      bundle.RID := r.RID.ref
+      bundle.RDATA := r.RDATA.ref
+      bundle.RRESP := r.RRESP.ref
+      bundle.RLAST := r.RLAST.ref
+      bundle.RUSER := r.RUSER.ref
+      bundle.RVALID := r.RVALID.ref
+      // IP -> Sim
+      r.RREADY.ref := bundle.RREADY
   }
 }
diff --git a/ipemu/src/dpi/AXI.scala b/ipemu/src/dpi/AXI.scala
new file mode 100644
index 000000000..03fd58a14
--- /dev/null
+++ b/ipemu/src/dpi/AXI.scala
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
+
+package org.chipsalliance.t1.ipemu.dpi
+
+import chisel3._
+import org.chipsalliance.amba.axi4.bundle.AXI4RWIrrevocableVerilog
+
+class awDpi(channelName: String, bundle: AXI4RWIrrevocableVerilog, triggerDelay: Int) extends DPIModuleLegacy {
+  override def desiredName: String = channelName + '_' + super.desiredName
+  val isImport: Boolean = true
+  val clock = dpiTrigger("clock", Input(Bool()))
+
+  val AWID = dpiIn("AWID", bundle.AWID)
+  val AWADDR = dpiIn("AWADDR", bundle.AWADDR)
+  val AWLEN = dpiIn("AWLEN", bundle.AWLEN)
+  val AWSIZE = dpiIn("AWSIZE", bundle.AWSIZE)
+  val AWBURST = dpiIn("AWBURST", bundle.AWBURST)
+  val AWLOCK = dpiIn("AWLOCK", bundle.AWLOCK)
+  val AWCACHE = dpiIn("AWCACHE", bundle.AWCACHE)
+  val AWPROT = dpiIn("AWPROT", bundle.AWPROT)
+  val AWQOS = dpiIn("AWQOS", bundle.AWQOS)
+  val AWREGION = dpiIn("AWREGION", bundle.AWREGION)
+  val AWUSER = dpiIn("AWUSER", bundle.AWUSER)
+  val AWVALID = dpiIn("AWVALID", bundle.AWVALID)
+  val AWREADY = dpiOut("AWREADY", bundle.AWREADY)
+
+  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
+}
+
+class wDpi(channelName: String, bundle: AXI4RWIrrevocableVerilog, triggerDelay: Int) extends DPIModuleLegacy {
+  override def desiredName = channelName + '_' + super.desiredName
+  val isImport: Boolean = true
+  val clock = dpiTrigger("clock", Input(Bool()))
+
+  val WDATA = dpiIn("WDATA", bundle.WDATA)
+  val WSTRB = dpiIn("WSTRB", bundle.WSTRB)
+  val WLAST = dpiIn("WLAST", bundle.WLAST)
+  val WUSER = dpiIn("WUSER", bundle.WUSER)
+  val WVALID = dpiIn("WVALID", bundle.WVALID)
+  val WREADY = dpiOut("WREADY", bundle.WREADY)
+
+  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
+}
+
+class bDpi(channelName: String, bundle: AXI4RWIrrevocableVerilog, triggerDelay: Int) extends DPIModuleLegacy {
+  override def desiredName = channelName + '_' + super.desiredName
+  val isImport: Boolean = true
+  val clock = dpiTrigger("clock", Input(Bool()))
+
+  val BID = dpiOut("BID", bundle.BID)
+  val BRESP = dpiOut("BRESP", bundle.BRESP)
+  val BUSER = dpiOut("BUSER", bundle.BUSER)
+  val BVALID = dpiOut("BVALID", bundle.BVALID)
+  val BREADY = dpiIn("BREADY", bundle.BREADY)
+
+  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
+}
+
+class arDpi(channelName: String, bundle: AXI4RWIrrevocableVerilog, triggerDelay: Int) extends DPIModuleLegacy {
+  override def desiredName = channelName + '_' + super.desiredName
+  val isImport: Boolean = true
+  val clock = dpiTrigger("clock", Input(Bool()))
+
+  val ARID = dpiIn("ARID", bundle.ARID)
+  val ARADDR = dpiIn("ARADDR", bundle.ARADDR)
+  val ARLEN = dpiIn("ARLEN", bundle.ARLEN)
+  val ARSIZE = dpiIn("ARSIZE", bundle.ARSIZE)
+  val ARBURST = dpiIn("ARBURST", bundle.ARBURST)
+  val ARLOCK = dpiIn("ARLOCK", bundle.ARLOCK)
+  val ARCACHE = dpiIn("ARCACHE", bundle.ARCACHE)
+  val ARPROT = dpiIn("ARPROT", bundle.ARPROT)
+  val ARQOS = dpiIn("ARQOS", bundle.ARQOS)
+  val ARREGION = dpiIn("ARREGION", bundle.ARREGION)
+  val ARUSER = dpiIn("ARUSER", bundle.ARUSER)
+  val ARVALID = dpiIn("ARVALID", bundle.ARVALID)
+  val ARREADY = dpiOut("ARREADY", bundle.ARREADY)
+
+  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
+}
+
+class rDpi(channelName: String, bundle: AXI4RWIrrevocableVerilog, triggerDelay: Int) extends DPIModuleLegacy {
+  override def desiredName = channelName + '_' + super.desiredName
+  val isImport: Boolean = true
+  val clock = dpiTrigger("clock", Input(Bool()))
+
+  val RID = dpiOut("RID", bundle.RID)
+  val RDATA = dpiOut("RDATA", bundle.RDATA)
+  val RRESP = dpiOut("RRESP", bundle.RRESP)
+  val RLAST = dpiOut("RLAST", bundle.RLAST)
+  val RUSER = dpiOut("RUSER", bundle.RUSER)
+  val RVALID = dpiOut("RVALID", bundle.RVALID)
+  val RREADY = dpiIn("RREADY", bundle.RREADY)
+
+  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
+}
+
diff --git a/ipemu/src/dpi/PeekTL.scala b/ipemu/src/dpi/PeekTL.scala
deleted file mode 100644
index d02203640..000000000
--- a/ipemu/src/dpi/PeekTL.scala
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
-
-package org.chipsalliance.t1.ipemu.dpi
-
-import chisel3._
-
-import tilelink.TLBundle
-
-class PeekTL(bundle: TLBundle, triggerDelay: Int) extends DPIModuleLegacy {
-  val isImport: Boolean = true
-  val clock = dpiTrigger("clock", Input(Bool()))
-  val channel = dpiIn("channel", Input(UInt(32.W)))
-
-  val aBits = bundle.a.bits
-  val aBits_opcode = dpiIn("aBits_opcode", Input(aBits.opcode))
-  val aBits_param = dpiIn("aBits_param", Input(aBits.param))
-  val aBits_size = dpiIn("aBits_size", Input(aBits.size))
-  val aBits_source = dpiIn("aBits_source", Input(aBits.source))
-  val aBits_address = dpiIn("aBits_address", Input(aBits.address))
-  val aBits_mask = dpiIn("aBits_mask", Input(aBits.mask))
-  val aBits_data = dpiIn("aBits_data", Input(aBits.data))
-  val aBits_corrupt = dpiIn("aBits_corrupt", Input(aBits.corrupt))
-  val aValid = dpiIn("aValid", Input(bundle.a.valid))
-  val dReady = dpiIn("dReady", Input(bundle.d.ready))
-
-  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
-}
diff --git a/ipemu/src/dpi/PokeTL.scala b/ipemu/src/dpi/PokeTL.scala
deleted file mode 100644
index 0de43a9ba..000000000
--- a/ipemu/src/dpi/PokeTL.scala
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
-
-package org.chipsalliance.t1.ipemu.dpi
-
-import chisel3._
-
-import tilelink.TLBundle
-
-class PokeTL(bundle: TLBundle, triggerDelay: Int) extends DPIModuleLegacy {
-  val isImport: Boolean = true
-  val clock = dpiTrigger("clock", Input(Bool()))
-
-  val channel = dpiIn("channel", Input(UInt(32.W)))
-
-  val dBits = bundle.d.bits
-  val dBits_opcode = dpiOut("dBits_opcode", Output(dBits.opcode))
-  val dBits_param = dpiOut("dBits_param", Output(dBits.param))
-  val dBits_size = dpiOut("dBits_size", Output(dBits.size))
-  val dBits_source = dpiOut("dBits_source", Output(dBits.source))
-  val dBits_sink = dpiOut("dBits_sink", Output(dBits.sink))
-  val dBits_denied = dpiOut("dBits_denied", Output(dBits.denied))
-  val dBits_data = dpiOut("dBits_data", Output(dBits.data))
-  val dBits_corrupt = dpiOut("dBits_corrupt", Output(dBits.corrupt))
-
-  val dValid = dpiOut("dValid", Output(bundle.d.valid))
-  val aReady = dpiOut("aReady", Output(bundle.a.ready))
-  val dReady = dpiIn("dReady", Input(bundle.d.ready))
-
-  override val trigger = s"always @(posedge ${clock.name}) #(${triggerDelay})"
-}