Unresolved hierarchical reference

[CrazybinaryLi]

Error encountered when using the bind statement with SVA. The URL of the project is https://github.com/aytung94/DV_S2QED_RISCV/tree/master/rtl/mriscvcore . Parsing the yosys script (.ys) as follows:

plugin -i systemverilog

read_systemverilog -formal
./ALU/ALU.v
./DECO_INSTR/DECO_INSTR.v
./FSM/FSM.v
./IRQ/IRQ.v
./MEMORY_INTERFACE/MEMORY_INTERFACE.v
./MULT/MULT.v
.REG_FILE/REG_FILE.v
./UTILITIES/UTILITY.v
./mriscvcore.v
./rv32_opcodes.v
./jg_bind_wrapper.sv
./mriscvcore_top_s2qed.v ;

prep -top mriscvcore_top_s2qed;

hierarchy -check;

chformal -assume -early;

memory;

flatten;

sim -clock clk -resetn rstn -n 5 -rstlen 5 -zinit -w mriscvcore_top_s2qed;

setundef -undriven -expose;

write_btor fsm.btor2

Encountered an error: unresolved hierarchical reference