diff --git a/.github/workflows/large-designs.yml b/.github/workflows/large-designs.yml index 368a6d356..c3170f68c 100644 --- a/.github/workflows/large-designs.yml +++ b/.github/workflows/large-designs.yml @@ -487,13 +487,18 @@ jobs: **/plot_*.svg blackparrot_synth: - name: Black Parrot (synthesis) runs-on: [self-hosted, Linux, X64] container: ubuntu:jammy + strategy: + matrix: + vars: [ {cfg: e_bp_unicore_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_1_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_1_cce_ucode_cfg, machine: n2-highmem-8}, {cfg: e_bp_multicore_4_cfg, machine: n2-highmem-32}, {cfg: e_bp_multicore_4_cce_ucode_cfg, machine: n2-highmem-32} ] + fail-fast: false + name: Black Parrot (${{ matrix.vars.cfg }} - synthesis) env: CC: gcc-9 CXX: g++-9 DEBIAN_FRONTEND: noninteractive + GHA_MACHINE_TYPE: ${{ matrix.vars.machine }} steps: - uses: actions/checkout@v3 @@ -540,11 +545,12 @@ jobs: env: TARGET: uhdm/yosys/synth-blackparrot-build TEST_CASE: tests/black-parrot + BLACKPARROT_CFG: ${{ matrix.vars.cfg }} - uses: actions/upload-artifact@v2 with: - name: bp_unicore.edif - path: uhdm-tests/black-parrot/black-parrot/bp_top/syn/bp_unicore.edif + name: bp_${{ matrix.vars.cfg }}.edif + path: UHDM-integration-tests/build/bp_${{ matrix.vars.cfg }}.edif - name: Upload load graphs if: ${{ always() }} diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 7fa6cc39f..5acd55214 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -155,6 +155,7 @@ jobs: - name: Build binaries run: | export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" + cd yosys && git apply ../0001-Add-typedef-support-to-detectSignWidthWorker.patch && cd - ./build_binaries.sh # By default actions/upload-artifact@v2 do not preserve file permissions # tar directory to workaround this issue diff --git a/0001-Add-typedef-support-to-detectSignWidthWorker.patch b/0001-Add-typedef-support-to-detectSignWidthWorker.patch new file mode 100644 index 000000000..529ac6661 --- /dev/null +++ b/0001-Add-typedef-support-to-detectSignWidthWorker.patch @@ -0,0 +1,14 @@ +diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc +index eaf6553ce..ee7121548 100644 +--- a/frontends/ast/genrtlil.cc ++++ b/frontends/ast/genrtlil.cc +@@ -841,6 +841,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun + } + if (!id_ast) + log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str()); ++ if (id_ast->type == AST_TYPEDEF) { ++ id_ast = id_ast->children[0]; ++ } + if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) { + if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { + this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; diff --git a/uhdm-tests/black-parrot/Makefile.in b/uhdm-tests/black-parrot/Makefile.in index f346ca28e..ec97cb3fb 100644 --- a/uhdm-tests/black-parrot/Makefile.in +++ b/uhdm-tests/black-parrot/Makefile.in @@ -2,18 +2,27 @@ curr_dir:=$(dir $(lastword $(MAKEFILE_LIST))) ################### ### BLACKPARROT ### ################### -VENV_BLACKPARROT_SYNTH = ${root_dir}/venv-blackparrot-synth BLACKPARROT = ${curr_dir}/black-parrot +BLACKPARROT_PATCHES_DIR = ${curr_dir}/black-parrot-patches/black-parrot/ +BLACKPARROT_BASEJUMP = ${BLACKPARROT}/external/basejump_stl/ +BLACKPARROT_BASEJUMP_PATCHES_DIR = ${curr_dir}/black-parrot-patches/basejump_stl +BLACKPARROT_CFG ?= e_bp_unicore_cfg +BLACKPARROT_UHDM = ${root_dir}/build/surelog/bp_tethered.${BLACKPARROT_CFG}.none.parse/out/slpp_unit/surelog.uhdm -${VENV_BLACKPARROT_SYNTH}: - virtualenv ${VENV_BLACKPARROT_SYNTH} - (. ${VENV_BLACKPARROT_SYNTH}/bin/activate) +${BLACKPARROT_BASEJUMP}/.gitpatch: + cd ${BLACKPARROT_BASEJUMP} && git apply ${BLACKPARROT_BASEJUMP_PATCHES_DIR}/*.patch && touch $@ -uhdm/yosys/synth-blackparrot-build: clean-build | ${VENV_BLACKPARROT_SYNTH} +${BLACKPARROT}/.gitpatch: | ${BLACKPARROT_BASEJUMP}/.gitpatch + cd ${BLACKPARROT}/ && git apply ${BLACKPARROT_PATCHES_DIR}/*.patch && touch $@ + +${BLACKPARROT_UHDM}: clean-build | ${BLACKPARROT}/.gitpatch + (export PATH=${root_dir}/../image/bin:${PATH} && \ + cd ${BLACKPARROT}/bp_top/syn/ && SURELOG_OPTS=-synth $(MAKE) parse.surelog CFG=${BLACKPARROT_CFG} RESULTS_PATH=${root_dir}/build) + +uhdm/yosys/synth-blackparrot-build: | ${BLACKPARROT_UHDM} (export PATH=${root_dir}/../image/bin:${PATH} && \ - . ${VENV_BLACKPARROT_SYNTH}/bin/activate && \ - cd ${BLACKPARROT}/bp_top/syn/ && SURELOG_OPTS=-synth $(MAKE) parse.surelog CFG=e_bp_unicore_cfg && \ + cd ${root_dir}/build && \ yosys -p "plugin -i systemverilog" \ - -p "read_uhdm ./results/surelog/bp_tethered.e_bp_unicore_cfg.none.parse/out/slpp_unit/surelog.uhdm" \ + -p "read_uhdm ${BLACKPARROT_UHDM}" \ -p "synth_xilinx -iopad -family xc7" \ - -p "write_edif bp_unicore.edif") + -p "write_edif bp_${BLACKPARROT_CFG}.edif") diff --git a/uhdm-tests/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch b/uhdm-tests/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch new file mode 100644 index 000000000..11d7d4cfa --- /dev/null +++ b/uhdm-tests/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch @@ -0,0 +1,93 @@ +From 638f88f8ea7f28d8f10d502033214ca6cc8cc696 Mon Sep 17 00:00:00 2001 +From: Kamil Rakoczy +Date: Wed, 26 Apr 2023 15:06:28 +0200 +Subject: [PATCH 3/3] WIP: start wires from index 0 + +Signed-off-by: Kamil Rakoczy +--- + bsg_noc/bsg_mesh_stitch.v | 51 ++++++++++++++++++++++----------------- + 1 file changed, 29 insertions(+), 22 deletions(-) + +diff --git a/bsg_noc/bsg_mesh_stitch.v b/bsg_noc/bsg_mesh_stitch.v +index 6ccb8383..201dce61 100644 +--- a/bsg_noc/bsg_mesh_stitch.v ++++ b/bsg_noc/bsg_mesh_stitch.v +@@ -14,15 +14,22 @@ module bsg_mesh_stitch + , x_max_p = "inv" + , y_max_p = "inv" + , nets_p = 1 // optional parameter that allows for multiple networks to be routed together ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) +- (input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] outs_i // for each node, each direction +- , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] ins_o ++ (input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] outs_i // for each node, each direction ++ , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] ins_o + + // these are the edge of the greater tile +- , input [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i +- , output [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o +- , input [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i +- , output [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o ++ , input [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i ++ , output [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o ++ , input [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i ++ , output [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o + ); + + genvar r,c,net; +@@ -32,30 +39,30 @@ module bsg_mesh_stitch + + for (r = 0; r < y_max_p; r=r+1) + begin: _r +- assign hor_o[E][r][net] = outs_i[r][x_max_p-1][net][E]; +- assign hor_o[W][r][net] = outs_i[r][0 ][net][W]; ++ assign hor_o[E2-1][r][net] = outs_i[r][x_max_p-1][net][E2-1]; ++ assign hor_o[W2][r][net] = outs_i[r][0 ][net][W2]; + + for (c = 0; c < x_max_p; c=c+1) + begin: _c +- assign ins_o[r][c][net][S] = (r == y_max_p-1) +- ? ver_i[S][c][net] +- : outs_i[(r == y_max_p-1) ? r : r+1][c][net][N]; // ?: for warning +- assign ins_o[r][c][net][N] = (r == 0) +- ? ver_i[N][c][net] +- : outs_i[r ? r-1: 0][c][net][S]; // ?: to eliminate warning +- assign ins_o[r][c][net][E] = (c == x_max_p-1) +- ? hor_i[E][r][net] +- : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W]; // ?: for warning +- assign ins_o[r][c][net][W] = (c == 0) +- ? hor_i[W][r][net] +- : outs_i[r][c ? (c-1) :0][net][E]; // ?: to eliminate warning ++ assign ins_o[r][c][net][N2] = (r == y_max_p-1) ++ ? ver_i[N2][c][net] ++ : outs_i[(r == y_max_p-1) ? r : r+1][c][net][S2]; // ?: for warning ++ assign ins_o[r][c][net][S2] = (r == 0) ++ ? ver_i[S2][c][net] ++ : outs_i[r ? r-1: 0][c][net][N2]; // ?: to eliminate warning ++ assign ins_o[r][c][net][E2-1] = (c == x_max_p-1) ++ ? hor_i[E2-1][r][net] ++ : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W2]; // ?: for warning ++ assign ins_o[r][c][net][W2] = (c == 0) ++ ? hor_i[W2][r][net] ++ : outs_i[r][c ? (c-1) :0][net][E2-1]; // ?: to eliminate warning + end // block: c + end // block: r + + for (c = 0; c < x_max_p; c=c+1) + begin: _c +- assign ver_o[S][c][net] = outs_i[y_max_p-1][c][net][S]; +- assign ver_o[N][c][net] = outs_i[0 ][c][net][N]; ++ assign ver_o[N2][c][net] = outs_i[y_max_p-1][c][net][N2]; ++ assign ver_o[S2][c][net] = outs_i[0 ][c][net][S2]; + end + end // block: _n + +-- +2.39.0 + diff --git a/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch b/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch new file mode 100644 index 000000000..b29360b3b --- /dev/null +++ b/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch @@ -0,0 +1,33 @@ +From 0a5300004fc90bae4b0dbc214ff331e5a25cd5a6 Mon Sep 17 00:00:00 2001 +From: Kamil Rakoczy +Date: Wed, 26 Apr 2023 09:17:48 +0200 +Subject: [PATCH 2/4] Add workaround for unsupported typespec + +Signed-off-by: Kamil Rakoczy +--- + bp_common/src/include/bp_common_bedrock_if.svh | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/bp_common/src/include/bp_common_bedrock_if.svh b/bp_common/src/include/bp_common_bedrock_if.svh +index ac7acf8f..5118d0ee 100644 +--- a/bp_common/src/include/bp_common_bedrock_if.svh ++++ b/bp_common/src/include/bp_common_bedrock_if.svh +@@ -196,10 +196,14 @@ + `declare_bp_bedrock_header_width(addr_width_mp, mem_fwd_payload_width_lp, mem_fwd) \ + `declare_bp_bedrock_header_width(addr_width_mp, mem_rev_payload_width_lp, mem_rev) + ++ //declare_bp_bedrock_mem_payload_s macro defines `bp_bedrock_mem_fwd_payload_s` struct, ++ //and creates typedef `bp_bedrock_mem_rev_payload_s` that is equal to ++ //`bp_bedrock_mem_fwd_payload_s` but Surelog doesn't see it. Use ++ //`bp_bedrock_mem_fwd_payload_s` directly for now. + `define declare_bp_bedrock_mem_if(addr_width_mp, did_width_mp, lce_id_width_mp, lce_assoc_mp) \ + `declare_bp_bedrock_mem_payload_s(did_width_mp, lce_id_width_mp, lce_assoc_mp); \ + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_fwd); \ +- `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_rev_payload_s, mem_rev) \ ++ `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_rev) \ + + `define declare_bp_bedrock_if_widths(addr_width_mp, payload_width_mp, name_mp) \ + , localparam ``name_mp``_msg_payload_width_lp = payload_width_mp \ +-- +2.39.0 + diff --git a/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0004-WIP-start-wires-from-index-0.patch b/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0004-WIP-start-wires-from-index-0.patch new file mode 100644 index 000000000..cd06dc1c1 --- /dev/null +++ b/uhdm-tests/black-parrot/black-parrot-patches/black-parrot/0004-WIP-start-wires-from-index-0.patch @@ -0,0 +1,1054 @@ +From a42626a8fdd6536fd57e4b33b93413b377507cfe Mon Sep 17 00:00:00 2001 +From: Kamil Rakoczy +Date: Wed, 26 Apr 2023 15:05:45 +0200 +Subject: [PATCH 4/4] WIP: start wires from index 0 + +Signed-off-by: Kamil Rakoczy +--- + bp_top/src/v/bp_cacc_complex.sv | 53 +++++---- + bp_top/src/v/bp_core_complex.sv | 83 +++++++------ + bp_top/src/v/bp_core_lite.sv | 190 +++++++++++++++--------------- + bp_top/src/v/bp_core_tile_node.sv | 23 ++-- + bp_top/src/v/bp_io_complex.sv | 49 ++++---- + bp_top/src/v/bp_io_tile_node.sv | 23 ++-- + bp_top/src/v/bp_mem_complex.sv | 65 +++++----- + bp_top/src/v/bp_multicore.sv | 90 +++++++------- + bp_top/src/v/bp_sacc_complex.sv | 31 +++-- + 9 files changed, 331 insertions(+), 276 deletions(-) + +diff --git a/bp_top/src/v/bp_cacc_complex.sv b/bp_top/src/v/bp_cacc_complex.sv +index 073aa544..83575666 100644 +--- a/bp_top/src/v/bp_cacc_complex.sv ++++ b/bp_top/src/v/bp_cacc_complex.sv +@@ -12,6 +12,13 @@ module bp_cacc_complex + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input core_reset_i +@@ -34,21 +41,21 @@ module bp_cacc_complex + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + +- bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; +- bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_req_ver_link_li, lce_req_ver_link_lo; ++ bp_coh_ready_and_link_s [cac_y_dim_p-1:0][SW2:0] lce_req_link_li, lce_req_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_req_ver_link_li, lce_req_ver_link_lo; + +- bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; +- bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; ++ bp_coh_ready_and_link_s [cac_y_dim_p-1:0][SW2:0] lce_cmd_link_li, lce_cmd_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + +- bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_fill_link_li, lce_fill_link_lo; +- bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_fill_ver_link_li, lce_fill_ver_link_lo; ++ bp_coh_ready_and_link_s [cac_y_dim_p-1:0][SW2:0] lce_fill_link_li, lce_fill_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cac_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_fill_ver_link_li, lce_fill_ver_link_lo; + +- bp_coh_ready_and_link_s [cac_y_dim_p-1:0][S:W] lce_resp_link_li, lce_resp_link_lo; +- bp_coh_ready_and_link_s [E:W][cac_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_resp_ver_link_li, lce_resp_ver_link_lo; ++ bp_coh_ready_and_link_s [cac_y_dim_p-1:0][SW2:0] lce_resp_link_li, lce_resp_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cac_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_resp_ver_link_li, lce_resp_ver_link_lo; + + + for (genvar j=0; j < cac_y_dim_p; j++) +@@ -92,8 +99,8 @@ module bp_cacc_complex + if (cac_x_dim_p > 0) + begin : ac_stitch + assign lce_req_ver_link_li = '0; +- assign lce_req_hor_link_li[E] = '0; +- assign lce_req_hor_link_li[W] = coh_req_link_i; ++ assign lce_req_hor_link_li[E2-1] = '0; ++ assign lce_req_hor_link_li[W2] = coh_req_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -109,11 +116,11 @@ module bp_cacc_complex + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); +- assign coh_req_link_o = lce_req_hor_link_lo[W]; ++ assign coh_req_link_o = lce_req_hor_link_lo[W2]; + + assign lce_cmd_ver_link_li = '0; +- assign lce_cmd_hor_link_li[E] = '0; +- assign lce_cmd_hor_link_li[W] = coh_cmd_link_i; ++ assign lce_cmd_hor_link_li[E2-1] = '0; ++ assign lce_cmd_hor_link_li[W2] = coh_cmd_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -132,8 +139,8 @@ module bp_cacc_complex + assign coh_cmd_link_o = lce_cmd_hor_link_lo[W]; + + assign lce_fill_ver_link_li = '0; +- assign lce_fill_hor_link_li[E] = '0; +- assign lce_fill_hor_link_li[W] = coh_fill_link_i; ++ assign lce_fill_hor_link_li[E2-1] = '0; ++ assign lce_fill_hor_link_li[W2] = coh_fill_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -149,11 +156,11 @@ module bp_cacc_complex + ,.ver_i(lce_fill_ver_link_li) + ,.ver_o(lce_fill_ver_link_lo) + ); +- assign coh_fill_link_o = lce_fill_hor_link_lo[W]; ++ assign coh_fill_link_o = lce_fill_hor_link_lo[W2]; + + assign lce_resp_ver_link_li = '0; +- assign lce_resp_hor_link_li[E] = '0; +- assign lce_resp_hor_link_li[W] = coh_resp_link_i; ++ assign lce_resp_hor_link_li[E2-1] = '0; ++ assign lce_resp_hor_link_li[W2] = coh_resp_link_i; + + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -169,7 +176,7 @@ module bp_cacc_complex + ,.ver_i(lce_resp_ver_link_li) + ,.ver_o(lce_resp_ver_link_lo) + ); +- assign coh_resp_link_o = lce_resp_hor_link_lo[W]; ++ assign coh_resp_link_o = lce_resp_hor_link_lo[W2]; + + end + else +diff --git a/bp_top/src/v/bp_core_complex.sv b/bp_top/src/v/bp_core_complex.sv +index e1f24ff8..6c584363 100644 +--- a/bp_top/src/v/bp_core_complex.sv ++++ b/bp_top/src/v/bp_core_complex.sv +@@ -20,6 +20,13 @@ module bp_core_complex + + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input rt_clk_i +@@ -34,59 +41,59 @@ module bp_core_complex + , input [io_noc_did_width_p-1:0] my_did_i + , input [io_noc_did_width_p-1:0] host_did_i + +- , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_i +- , output [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_o ++ , input [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_i ++ , output [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_hor_link_o + +- , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_i +- , output [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_o ++ , input [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_i ++ , output [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_hor_link_o + +- , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_i +- , output [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_o ++ , input [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_i ++ , output [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_hor_link_o + +- , input [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_i +- , output [E:W][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_o ++ , input [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_i ++ , output [E2:W2][cc_y_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_hor_link_o + +- , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_i +- , output [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_o ++ , input [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_i ++ , output [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_req_ver_link_o + +- , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_i +- , output [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_o ++ , input [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_i ++ , output [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_ver_link_o + +- , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_i +- , output [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_o ++ , input [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_i ++ , output [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_fill_ver_link_o + +- , input [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_i +- , output [S:N][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_o ++ , input [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_i ++ , output [N2:S2][cc_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_resp_ver_link_o + +- , input [N:N][cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_fwd_ver_link_i +- , output [S:S][cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_fwd_ver_link_o ++ , input [cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_fwd_ver_link_i ++ , output [cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_fwd_ver_link_o + +- , input [S:S][cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_rev_ver_link_i +- , output [N:N][cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_rev_ver_link_o ++ , input [cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_rev_ver_link_i ++ , output [cc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_rev_ver_link_o + ); + + `declare_bp_cfg_bus_s(vaddr_width_p, hio_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p); + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, coh_noc_ral_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, mem_noc_ral_link_s); + +- coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_req_link_lo, lce_req_link_li; +- coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_cmd_link_lo, lce_cmd_link_li; +- coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_fill_link_lo, lce_fill_link_li; +- coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] lce_resp_link_lo, lce_resp_link_li; ++ coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][SW:0] lce_req_link_lo, lce_req_link_li; ++ coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][SW:0] lce_cmd_link_lo, lce_cmd_link_li; ++ coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][SW:0] lce_fill_link_lo, lce_fill_link_li; ++ coh_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][SW:0] lce_resp_link_lo, lce_resp_link_li; + +- mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:S] mem_fwd_link_lo, mem_rev_link_li; +- mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][N:N] mem_rev_link_lo, mem_fwd_link_li; ++ mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0] mem_fwd_link_lo, mem_rev_link_li; ++ mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0] mem_rev_link_lo, mem_fwd_link_li; + +- coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; +- coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; +- coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; +- coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; +- coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; +- coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_fill_ver_link_li, lce_fill_ver_link_lo; +- coh_noc_ral_link_s [E:W][cc_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; +- coh_noc_ral_link_s [S:N][cc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; ++ coh_noc_ral_link_s [E2:W2][cc_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; ++ coh_noc_ral_link_s [N2:S2][cc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; ++ coh_noc_ral_link_s [E2:W2][cc_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; ++ coh_noc_ral_link_s [N2:S2][cc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; ++ coh_noc_ral_link_s [E2:W2][cc_y_dim_p-1:0] lce_fill_hor_link_li, lce_fill_hor_link_lo; ++ coh_noc_ral_link_s [N2:S2][cc_x_dim_p-1:0] lce_fill_ver_link_li, lce_fill_ver_link_lo; ++ coh_noc_ral_link_s [E2:W2][cc_y_dim_p-1:0] lce_resp_hor_link_li, lce_resp_hor_link_lo; ++ coh_noc_ral_link_s [N2:S2][cc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; + +- mem_noc_ral_link_s [S:N][cc_x_dim_p-1:0] mem_ver_link_lo, mem_ver_link_li; ++ mem_noc_ral_link_s [N2:S2][cc_x_dim_p-1:0] mem_ver_link_lo, mem_ver_link_li; + + for (genvar j = 0; j < cc_y_dim_p; j++) + begin : y +@@ -207,12 +214,12 @@ module bp_core_complex + assign coh_resp_hor_link_o = lce_resp_hor_link_lo; + assign coh_resp_ver_link_o = lce_resp_ver_link_lo; + +- mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][S:W] mem_mesh_lo, mem_mesh_li; ++ mem_noc_ral_link_s [cc_y_dim_p-1:0][cc_x_dim_p-1:0][SW:0] mem_mesh_lo, mem_mesh_li; + for (genvar i = 0; i < cc_y_dim_p; i++) + for (genvar j = 0; j < cc_x_dim_p; j++) + begin : link +- assign mem_mesh_lo[i][j][S] = mem_fwd_link_lo[i][j]; +- assign mem_mesh_lo[i][j][N] = mem_rev_link_lo[i][j]; ++ assign mem_mesh_lo[i][j][N2] = mem_fwd_link_lo[i][j]; ++ assign mem_mesh_lo[i][j][S2] = mem_rev_link_lo[i][j]; + + assign mem_fwd_link_li[i][j] = mem_mesh_li[i][j][N]; + assign mem_rev_link_li[i][j] = mem_mesh_li[i][j][S]; +diff --git a/bp_top/src/v/bp_core_lite.sv b/bp_top/src/v/bp_core_lite.sv +index 4fe0675f..f3b9ed4b 100644 +--- a/bp_top/src/v/bp_core_lite.sv ++++ b/bp_top/src/v/bp_core_lite.sv +@@ -294,50 +294,50 @@ module bp_core_lite + ,.lce_resp_data_ready_and_i(lce_resp_data_ready_and_i[0]) + ); + +- logic [1:1][lce_req_header_width_lp-1:0] _lce_req_header_o; +- logic [1:1] _lce_req_header_v_o; +- logic [1:1] _lce_req_header_ready_and_i; +- logic [1:1] _lce_req_has_data_o; +- logic [1:1][icache_fill_width_p-1:0] _lce_req_data_o; +- logic [1:1] _lce_req_data_v_o; +- logic [1:1] _lce_req_data_ready_and_i; +- logic [1:1] _lce_req_last_o; +- +- logic [1:1][lce_cmd_header_width_lp-1:0] _lce_cmd_header_i; +- logic [1:1] _lce_cmd_header_v_i; +- logic [1:1] _lce_cmd_header_ready_and_o; +- logic [1:1] _lce_cmd_has_data_i; +- logic [1:1][icache_fill_width_p-1:0] _lce_cmd_data_i; +- logic [1:1] _lce_cmd_data_v_i; +- logic [1:1] _lce_cmd_data_ready_and_o; +- logic [1:1] _lce_cmd_last_i; +- +- logic [1:1][lce_fill_header_width_lp-1:0] _lce_fill_header_i; +- logic [1:1] _lce_fill_header_v_i; +- logic [1:1] _lce_fill_header_ready_and_o; +- logic [1:1] _lce_fill_has_data_i; +- logic [1:1][icache_fill_width_p-1:0] _lce_fill_data_i; +- logic [1:1] _lce_fill_data_v_i; +- logic [1:1] _lce_fill_data_ready_and_o; +- logic [1:1] _lce_fill_last_i; +- +- logic [1:1][lce_fill_header_width_lp-1:0] _lce_fill_header_o; +- logic [1:1] _lce_fill_header_v_o; +- logic [1:1] _lce_fill_header_ready_and_i; +- logic [1:1] _lce_fill_has_data_o; +- logic [1:1][icache_fill_width_p-1:0] _lce_fill_data_o; +- logic [1:1] _lce_fill_data_v_o; +- logic [1:1] _lce_fill_data_ready_and_i; +- logic [1:1] _lce_fill_last_o; +- +- logic [1:1][lce_resp_header_width_lp-1:0] _lce_resp_header_o; +- logic [1:1] _lce_resp_header_v_o; +- logic [1:1] _lce_resp_header_ready_and_i; +- logic [1:1] _lce_resp_has_data_o; +- logic [1:1][icache_fill_width_p-1:0] _lce_resp_data_o; +- logic [1:1] _lce_resp_data_v_o; +- logic [1:1] _lce_resp_data_ready_and_i; +- logic [1:1] _lce_resp_last_o; ++ logic [lce_req_header_width_lp-1:0] _lce_req_header_o; ++ logic _lce_req_header_v_o; ++ logic _lce_req_header_ready_and_i; ++ logic _lce_req_has_data_o; ++ logic [icache_fill_width_p-1:0] _lce_req_data_o; ++ logic _lce_req_data_v_o; ++ logic _lce_req_data_ready_and_i; ++ logic _lce_req_last_o; ++ ++ logic [lce_cmd_header_width_lp-1:0] _lce_cmd_header_i; ++ logic _lce_cmd_header_v_i; ++ logic _lce_cmd_header_ready_and_o; ++ logic _lce_cmd_has_data_i; ++ logic [icache_fill_width_p-1:0] _lce_cmd_data_i; ++ logic _lce_cmd_data_v_i; ++ logic _lce_cmd_data_ready_and_o; ++ logic _lce_cmd_last_i; ++ ++ logic [lce_fill_header_width_lp-1:0] _lce_fill_header_i; ++ logic _lce_fill_header_v_i; ++ logic _lce_fill_header_ready_and_o; ++ logic _lce_fill_has_data_i; ++ logic [icache_fill_width_p-1:0] _lce_fill_data_i; ++ logic _lce_fill_data_v_i; ++ logic _lce_fill_data_ready_and_o; ++ logic _lce_fill_last_i; ++ ++ logic [lce_fill_header_width_lp-1:0] _lce_fill_header_o; ++ logic _lce_fill_header_v_o; ++ logic _lce_fill_header_ready_and_i; ++ logic _lce_fill_has_data_o; ++ logic [icache_fill_width_p-1:0] _lce_fill_data_o; ++ logic _lce_fill_data_v_o; ++ logic _lce_fill_data_ready_and_i; ++ logic _lce_fill_last_o; ++ ++ logic [lce_resp_header_width_lp-1:0] _lce_resp_header_o; ++ logic _lce_resp_header_v_o; ++ logic _lce_resp_header_ready_and_i; ++ logic _lce_resp_has_data_o; ++ logic [icache_fill_width_p-1:0] _lce_resp_data_o; ++ logic _lce_resp_data_v_o; ++ logic _lce_resp_data_ready_and_i; ++ logic _lce_resp_last_o; + bp_lce + #(.bp_params_p(bp_params_p) + ,.assoc_p(dcache_assoc_p) +@@ -383,50 +383,50 @@ module bp_core_lite + ,.stat_mem_pkt_yumi_i(dcache_stat_mem_pkt_yumi_lo) + ,.stat_mem_i(dcache_stat_mem_lo) + +- ,.lce_req_header_o(_lce_req_header_o[1]) +- ,.lce_req_header_v_o(_lce_req_header_v_o[1]) +- ,.lce_req_has_data_o(_lce_req_has_data_o[1]) +- ,.lce_req_header_ready_and_i(_lce_req_header_ready_and_i[1]) +- ,.lce_req_data_o(_lce_req_data_o[1]) +- ,.lce_req_data_v_o(_lce_req_data_v_o[1]) +- ,.lce_req_last_o(_lce_req_last_o[1]) +- ,.lce_req_data_ready_and_i(_lce_req_data_ready_and_i[1]) +- +- ,.lce_cmd_header_i(_lce_cmd_header_i[1]) +- ,.lce_cmd_header_v_i(_lce_cmd_header_v_i[1]) +- ,.lce_cmd_has_data_i(_lce_cmd_has_data_i[1]) +- ,.lce_cmd_header_ready_and_o(_lce_cmd_header_ready_and_o[1]) +- ,.lce_cmd_data_i(_lce_cmd_data_i[1]) +- ,.lce_cmd_data_v_i(_lce_cmd_data_v_i[1]) +- ,.lce_cmd_last_i(_lce_cmd_last_i[1]) +- ,.lce_cmd_data_ready_and_o(_lce_cmd_data_ready_and_o[1]) +- +- ,.lce_fill_header_i(_lce_fill_header_i[1]) +- ,.lce_fill_header_v_i(_lce_fill_header_v_i[1]) +- ,.lce_fill_has_data_i(_lce_fill_has_data_i[1]) +- ,.lce_fill_header_ready_and_o(_lce_fill_header_ready_and_o[1]) +- ,.lce_fill_data_i(_lce_fill_data_i[1]) +- ,.lce_fill_data_v_i(_lce_fill_data_v_i[1]) +- ,.lce_fill_last_i(_lce_fill_last_i[1]) +- ,.lce_fill_data_ready_and_o(_lce_fill_data_ready_and_o[1]) +- +- ,.lce_fill_header_o(_lce_fill_header_o[1]) +- ,.lce_fill_header_v_o(_lce_fill_header_v_o[1]) +- ,.lce_fill_has_data_o(_lce_fill_has_data_o[1]) +- ,.lce_fill_header_ready_and_i(_lce_fill_header_ready_and_i[1]) +- ,.lce_fill_data_o(_lce_fill_data_o[1]) +- ,.lce_fill_data_v_o(_lce_fill_data_v_o[1]) +- ,.lce_fill_last_o(_lce_fill_last_o[1]) +- ,.lce_fill_data_ready_and_i(_lce_fill_data_ready_and_i[1]) +- +- ,.lce_resp_header_o(_lce_resp_header_o[1]) +- ,.lce_resp_header_v_o(_lce_resp_header_v_o[1]) +- ,.lce_resp_has_data_o(_lce_resp_has_data_o[1]) +- ,.lce_resp_header_ready_and_i(_lce_resp_header_ready_and_i[1]) +- ,.lce_resp_data_o(_lce_resp_data_o[1]) +- ,.lce_resp_data_v_o(_lce_resp_data_v_o[1]) +- ,.lce_resp_last_o(_lce_resp_last_o[1]) +- ,.lce_resp_data_ready_and_i(_lce_resp_data_ready_and_i[1]) ++ ,.lce_req_header_o(_lce_req_header_o) ++ ,.lce_req_header_v_o(_lce_req_header_v_o) ++ ,.lce_req_has_data_o(_lce_req_has_data_o) ++ ,.lce_req_header_ready_and_i(_lce_req_header_ready_and_i) ++ ,.lce_req_data_o(_lce_req_data_o) ++ ,.lce_req_data_v_o(_lce_req_data_v_o) ++ ,.lce_req_last_o(_lce_req_last_o) ++ ,.lce_req_data_ready_and_i(_lce_req_data_ready_and_i) ++ ++ ,.lce_cmd_header_i(_lce_cmd_header_i) ++ ,.lce_cmd_header_v_i(_lce_cmd_header_v_i) ++ ,.lce_cmd_has_data_i(_lce_cmd_has_data_i) ++ ,.lce_cmd_header_ready_and_o(_lce_cmd_header_ready_and_o) ++ ,.lce_cmd_data_i(_lce_cmd_data_i) ++ ,.lce_cmd_data_v_i(_lce_cmd_data_v_i) ++ ,.lce_cmd_last_i(_lce_cmd_last_i) ++ ,.lce_cmd_data_ready_and_o(_lce_cmd_data_ready_and_o) ++ ++ ,.lce_fill_header_i(_lce_fill_header_i) ++ ,.lce_fill_header_v_i(_lce_fill_header_v_i) ++ ,.lce_fill_has_data_i(_lce_fill_has_data_i) ++ ,.lce_fill_header_ready_and_o(_lce_fill_header_ready_and_o) ++ ,.lce_fill_data_i(_lce_fill_data_i) ++ ,.lce_fill_data_v_i(_lce_fill_data_v_i) ++ ,.lce_fill_last_i(_lce_fill_last_i) ++ ,.lce_fill_data_ready_and_o(_lce_fill_data_ready_and_o) ++ ++ ,.lce_fill_header_o(_lce_fill_header_o) ++ ,.lce_fill_header_v_o(_lce_fill_header_v_o) ++ ,.lce_fill_has_data_o(_lce_fill_has_data_o) ++ ,.lce_fill_header_ready_and_i(_lce_fill_header_ready_and_i) ++ ,.lce_fill_data_o(_lce_fill_data_o) ++ ,.lce_fill_data_v_o(_lce_fill_data_v_o) ++ ,.lce_fill_last_o(_lce_fill_last_o) ++ ,.lce_fill_data_ready_and_i(_lce_fill_data_ready_and_i) ++ ++ ,.lce_resp_header_o(_lce_resp_header_o) ++ ,.lce_resp_header_v_o(_lce_resp_header_v_o) ++ ,.lce_resp_has_data_o(_lce_resp_has_data_o) ++ ,.lce_resp_header_ready_and_i(_lce_resp_header_ready_and_i) ++ ,.lce_resp_data_o(_lce_resp_data_o) ++ ,.lce_resp_data_v_o(_lce_resp_data_v_o) ++ ,.lce_resp_last_o(_lce_resp_last_o) ++ ,.lce_resp_data_ready_and_i(_lce_resp_data_ready_and_i) + ); + + bsg_edge_extend +@@ -434,15 +434,15 @@ module bp_core_lite + posedge_extend + (.clk_i(posedge_clk) + ,.reset_i(reset_i) +- ,.data_i({_lce_req_header_o[1], _lce_req_header_v_o[1], _lce_req_has_data_o[1], _lce_req_data_o[1], _lce_req_data_v_o[1], _lce_req_last_o[1] +- ,_lce_fill_header_o[1], _lce_fill_header_v_o[1], _lce_fill_has_data_o[1], _lce_fill_data_o[1], _lce_fill_data_v_o[1], _lce_fill_last_o[1] +- ,_lce_resp_header_o[1], _lce_resp_header_v_o[1], _lce_resp_has_data_o[1], _lce_resp_data_o[1], _lce_resp_data_v_o[1], _lce_resp_last_o[1] ++ ,.data_i({_lce_req_header_o, _lce_req_header_v_o, _lce_req_has_data_o, _lce_req_data_o, _lce_req_data_v_o, _lce_req_last_o ++ ,_lce_fill_header_o, _lce_fill_header_v_o, _lce_fill_has_data_o, _lce_fill_data_o, _lce_fill_data_v_o, _lce_fill_last_o ++ ,_lce_resp_header_o, _lce_resp_header_v_o, _lce_resp_has_data_o, _lce_resp_data_o, _lce_resp_data_v_o, _lce_resp_last_o + ,lce_req_header_ready_and_i[1], lce_req_data_ready_and_i[1], lce_fill_header_ready_and_i[1], lce_fill_data_ready_and_i[1], lce_resp_header_ready_and_i[1], lce_resp_data_ready_and_i[1] + }) + ,.data_o({lce_req_header_o[1], lce_req_header_v_o[1], lce_req_has_data_o[1], lce_req_data_o[1], lce_req_data_v_o[1], lce_req_last_o[1] + ,lce_fill_header_o[1], lce_fill_header_v_o[1], lce_fill_has_data_o[1], lce_fill_data_o[1], lce_fill_data_v_o[1], lce_fill_last_o[1] + ,lce_resp_header_o[1], lce_resp_header_v_o[1], lce_resp_has_data_o[1], lce_resp_data_o[1], lce_resp_data_v_o[1], lce_resp_last_o[1] +- ,_lce_req_header_ready_and_i[1], _lce_req_data_ready_and_i[1], _lce_fill_header_ready_and_i[1], _lce_fill_data_ready_and_i[1], _lce_resp_header_ready_and_i[1], _lce_resp_data_ready_and_i[1] ++ ,_lce_req_header_ready_and_i, _lce_req_data_ready_and_i, _lce_fill_header_ready_and_i, _lce_fill_data_ready_and_i, _lce_resp_header_ready_and_i, _lce_resp_data_ready_and_i + }) + ); + +@@ -453,10 +453,10 @@ module bp_core_lite + ,.reset_i(reset_i) + ,.data_i({lce_cmd_header_i[1], lce_cmd_header_v_i[1], lce_cmd_has_data_i[1], lce_cmd_data_i[1], lce_cmd_data_v_i[1], lce_cmd_last_i[1] + ,lce_fill_header_i[1], lce_fill_header_v_i[1], lce_fill_has_data_i[1], lce_fill_data_i[1], lce_fill_data_v_i[1], lce_fill_last_i[1] +- ,_lce_cmd_header_ready_and_o[1], _lce_cmd_data_ready_and_o[1], _lce_fill_header_ready_and_o[1], _lce_fill_data_ready_and_o[1] ++ ,_lce_cmd_header_ready_and_o, _lce_cmd_data_ready_and_o, _lce_fill_header_ready_and_o, _lce_fill_data_ready_and_o + }) +- ,.data_o({_lce_cmd_header_i[1], _lce_cmd_header_v_i[1], _lce_cmd_has_data_i[1], _lce_cmd_data_i[1], _lce_cmd_data_v_i[1], _lce_cmd_last_i[1] +- ,_lce_fill_header_i[1], _lce_fill_header_v_i[1], _lce_fill_has_data_i[1], _lce_fill_data_i[1], _lce_fill_data_v_i[1], _lce_fill_last_i[1] ++ ,.data_o({_lce_cmd_header_i, _lce_cmd_header_v_i, _lce_cmd_has_data_i, _lce_cmd_data_i, _lce_cmd_data_v_i, _lce_cmd_last_i ++ ,_lce_fill_header_i, _lce_fill_header_v_i, _lce_fill_has_data_i, _lce_fill_data_i, _lce_fill_data_v_i, _lce_fill_last_i + ,lce_cmd_header_ready_and_o[1], lce_cmd_data_ready_and_o[1], lce_fill_header_ready_and_o[1], lce_fill_data_ready_and_o[1] + }) + ); +diff --git a/bp_top/src/v/bp_core_tile_node.sv b/bp_top/src/v/bp_core_tile_node.sv +index 6d37ea15..d992121d 100644 +--- a/bp_top/src/v/bp_core_tile_node.sv ++++ b/bp_top/src/v/bp_core_tile_node.sv +@@ -19,6 +19,13 @@ module bp_core_tile_node + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input rt_clk_i +@@ -36,17 +43,17 @@ module bp_core_tile_node + , input [coh_noc_cord_width_p-1:0] my_cord_i + + // Connected to other tiles on east and west +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o ++ , input [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i ++ , output [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o ++ , input [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i ++ , output [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_o ++ , input [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_i ++ , output [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_fill_link_o + +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o ++ , input [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i ++ , output [SW2:0][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o + + , input [mem_noc_ral_link_width_lp-1:0] mem_fwd_link_i + , output [mem_noc_ral_link_width_lp-1:0] mem_fwd_link_o +diff --git a/bp_top/src/v/bp_io_complex.sv b/bp_top/src/v/bp_io_complex.sv +index d1eb12c7..7ab31834 100644 +--- a/bp_top/src/v/bp_io_complex.sv ++++ b/bp_top/src/v/bp_io_complex.sv +@@ -13,6 +13,13 @@ module bp_io_complex + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam io_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(io_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input core_reset_i +@@ -32,21 +39,21 @@ module bp_io_complex + , input [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_i + , output [ic_x_dim_p-1:0][coh_noc_ral_link_width_lp-1:0] coh_cmd_link_o + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_o + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(io_noc_flit_width_p, bp_io_ready_and_link_s); + +- bp_io_ready_and_link_s [ic_x_dim_p-1:0][E:W] io_fwd_link_li, io_fwd_link_lo, io_rev_link_li, io_rev_link_lo; +- bp_io_ready_and_link_s [E:W] io_fwd_hor_link_li, io_fwd_hor_link_lo, io_rev_hor_link_li, io_rev_hor_link_lo; +- bp_coh_ready_and_link_s [ic_x_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo, lce_cmd_link_li, lce_cmd_link_lo; +- bp_coh_ready_and_link_s [S:N][ic_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo, lce_cmd_ver_link_li, lce_cmd_ver_link_lo; +- bp_coh_ready_and_link_s [E:W] lce_req_hor_link_li, lce_req_hor_link_lo, lce_cmd_hor_link_li, lce_cmd_hor_link_lo; ++ bp_io_ready_and_link_s [ic_x_dim_p-1:0][E2:W2] io_fwd_link_li, io_fwd_link_lo, io_rev_link_li, io_rev_link_lo; ++ bp_io_ready_and_link_s [E2:W2] io_fwd_hor_link_li, io_fwd_hor_link_lo, io_rev_hor_link_li, io_rev_hor_link_lo; ++ bp_coh_ready_and_link_s [ic_x_dim_p-1:0][SW:0] lce_req_link_li, lce_req_link_lo, lce_cmd_link_li, lce_cmd_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][ic_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo, lce_cmd_ver_link_li, lce_cmd_ver_link_lo; ++ bp_coh_ready_and_link_s [E2:W2] lce_req_hor_link_li, lce_req_hor_link_lo, lce_cmd_hor_link_li, lce_cmd_hor_link_lo; + + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : node +@@ -81,8 +88,8 @@ module bp_io_complex + ); + end + +- assign lce_req_ver_link_li[N] = '0; +- assign lce_req_ver_link_li[S] = coh_req_link_i; ++ assign lce_req_ver_link_li[S2] = '0; ++ assign lce_req_ver_link_li[N2-1] = coh_req_link_i; + assign lce_req_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -98,10 +105,10 @@ module bp_io_complex + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); +- assign coh_req_link_o = lce_req_ver_link_lo[S]; ++ assign coh_req_link_o = lce_req_ver_link_lo[N2-1]; + +- assign lce_cmd_ver_link_li[N] = '0; +- assign lce_cmd_ver_link_li[S] = coh_cmd_link_i; ++ assign lce_cmd_ver_link_li[S2] = '0; ++ assign lce_cmd_ver_link_li[N2-1] = coh_cmd_link_i; + assign lce_cmd_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -117,13 +124,13 @@ module bp_io_complex + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); +- assign coh_cmd_link_o = lce_cmd_ver_link_lo[S]; ++ assign coh_cmd_link_o = lce_cmd_ver_link_lo[N2-1]; + +- bp_io_ready_and_link_s [ic_x_dim_p-1:0][S:W] io_fwd_mesh_lo, io_fwd_mesh_li; ++ bp_io_ready_and_link_s [ic_x_dim_p-1:0][SW:0] io_fwd_mesh_lo, io_fwd_mesh_li; + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : cmd_link +- assign io_fwd_mesh_lo[i][E:W] = io_fwd_link_lo[i][E:W]; +- assign io_fwd_link_li[i][E:W] = io_fwd_mesh_li[i][E:W]; ++ assign io_fwd_mesh_lo[i][E2:W2] = io_fwd_link_lo[i][E2:W2]; ++ assign io_fwd_link_li[i][E2:W2] = io_fwd_mesh_li[i][E2:W2]; + end + assign io_fwd_hor_link_li = io_fwd_link_i; + bsg_mesh_stitch +@@ -142,11 +149,11 @@ module bp_io_complex + ); + assign io_fwd_link_o = io_fwd_hor_link_lo; + +- bp_io_ready_and_link_s [ic_x_dim_p-1:0][S:W] io_rev_mesh_lo, io_rev_mesh_li; ++ bp_io_ready_and_link_s [ic_x_dim_p-1:0][SW:0] io_rev_mesh_lo, io_rev_mesh_li; + for (genvar i = 0; i < ic_x_dim_p; i++) + begin : resp_link +- assign io_rev_mesh_lo[i][E:W] = io_rev_link_lo[i][E:W]; +- assign io_rev_link_li[i][E:W] = io_rev_mesh_li[i][E:W]; ++ assign io_rev_mesh_lo[i][E2:W2] = io_rev_link_lo[i][E2:W2]; ++ assign io_rev_link_li[i][E2:W2] = io_rev_mesh_li[i][E2:W2]; + end + assign io_rev_hor_link_li = io_rev_link_i; + bsg_mesh_stitch +diff --git a/bp_top/src/v/bp_io_tile_node.sv b/bp_top/src/v/bp_io_tile_node.sv +index 1d6493a0..0fead623 100644 +--- a/bp_top/src/v/bp_io_tile_node.sv ++++ b/bp_top/src/v/bp_io_tile_node.sv +@@ -13,6 +13,13 @@ module bp_io_tile_node + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam io_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(io_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input core_reset_i +@@ -27,17 +34,17 @@ module bp_io_tile_node + , input [io_noc_did_width_p-1:0] host_did_i + , input [coh_noc_cord_width_p-1:0] my_cord_i + +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o ++ , input [SW:0][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i ++ , output [SW:0][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o + +- , input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i +- , output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o ++ , input [SW:0][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i ++ , output [SW:0][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_o + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_o + ); + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); +diff --git a/bp_top/src/v/bp_mem_complex.sv b/bp_top/src/v/bp_mem_complex.sv +index 956e4b8c..6287e24d 100644 +--- a/bp_top/src/v/bp_mem_complex.sv ++++ b/bp_top/src/v/bp_mem_complex.sv +@@ -13,6 +13,13 @@ module bp_mem_complex + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input core_reset_i +@@ -44,19 +51,19 @@ module bp_mem_complex + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_ready_and_link_s); + +- bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; +- bp_coh_ready_and_link_s [E:W] lce_req_hor_link_li, lce_req_hor_link_lo; +- bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; +- bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; +- bp_coh_ready_and_link_s [E:W] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; +- bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; +- bp_coh_ready_and_link_s [mc_x_dim_p-1:0][S:W] lce_resp_link_li, lce_resp_link_lo; +- bp_coh_ready_and_link_s [E:W] lce_resp_hor_link_li, lce_resp_hor_link_lo; +- bp_coh_ready_and_link_s [S:N][mc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; ++ bp_coh_ready_and_link_s [mc_x_dim_p-1:0][SW2:0] lce_req_link_li, lce_req_link_lo; ++ bp_coh_ready_and_link_s [E2:W2] lce_req_hor_link_li, lce_req_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][mc_x_dim_p-1:0] lce_req_ver_link_li, lce_req_ver_link_lo; ++ bp_coh_ready_and_link_s [mc_x_dim_p-1:0][SW2:0] lce_cmd_link_li, lce_cmd_link_lo; ++ bp_coh_ready_and_link_s [E2:W2] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][mc_x_dim_p-1:0] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; ++ bp_coh_ready_and_link_s [mc_x_dim_p-1:0][SW2:0] lce_resp_link_li, lce_resp_link_lo; ++ bp_coh_ready_and_link_s [E2:W2] lce_resp_hor_link_li, lce_resp_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][mc_x_dim_p-1:0] lce_resp_ver_link_li, lce_resp_ver_link_lo; + + bp_mem_ready_and_link_s [mc_x_dim_p-1:0] mem_fwd_link_li, mem_fwd_link_lo; + bp_mem_ready_and_link_s [mc_x_dim_p-1:0] mem_rev_link_li, mem_rev_link_lo; +- bp_mem_ready_and_link_s [S:N][mc_x_dim_p-1:0] mem_ver_link_li, mem_ver_link_lo; ++ bp_mem_ready_and_link_s [N2:S2][mc_x_dim_p-1:0] mem_ver_link_li, mem_ver_link_lo; + + for (genvar i = 0; i < mc_x_dim_p; i++) + begin : node +@@ -108,8 +115,8 @@ module bp_mem_complex + + if (mc_y_dim_p > 0) + begin : stitch +- assign lce_req_ver_link_li[N] = coh_req_link_i; +- assign lce_req_ver_link_li[S] = '0; ++ assign lce_req_ver_link_li[S2] = coh_req_link_i; ++ assign lce_req_ver_link_li[N2-1] = '0; + assign lce_req_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -125,10 +132,10 @@ module bp_mem_complex + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); +- assign coh_req_link_o = lce_req_ver_link_lo[N]; ++ assign coh_req_link_o = lce_req_ver_link_lo[S2]; + +- assign lce_cmd_ver_link_li[N] = coh_cmd_link_i; +- assign lce_cmd_ver_link_li[S] = '0; ++ assign lce_cmd_ver_link_li[S2] = coh_cmd_link_i; ++ assign lce_cmd_ver_link_li[N2-1] = '0; + assign lce_cmd_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -144,10 +151,10 @@ module bp_mem_complex + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); +- assign coh_cmd_link_o = lce_cmd_ver_link_lo[N]; ++ assign coh_cmd_link_o = lce_cmd_ver_link_lo[S2]; + +- assign lce_resp_ver_link_li[N] = coh_resp_link_i; +- assign lce_resp_ver_link_li[S] = '0; ++ assign lce_resp_ver_link_li[S2] = coh_resp_link_i; ++ assign lce_resp_ver_link_li[N2-1] = '0; + assign lce_resp_hor_link_li = '0; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) +@@ -163,18 +170,18 @@ module bp_mem_complex + ,.ver_i(lce_resp_ver_link_li) + ,.ver_o(lce_resp_ver_link_lo) + ); +- assign coh_resp_link_o = lce_resp_ver_link_lo[N]; ++ assign coh_resp_link_o = lce_resp_ver_link_lo[S2]; + + bp_mem_ready_and_link_s [mc_x_dim_p-1:0][S:W] mem_mesh_lo, mem_mesh_li; + for (genvar j = 0; j < mc_x_dim_p; j++) + begin : link +- assign mem_mesh_lo[j][S] = mem_fwd_link_lo[j]; +- assign mem_mesh_lo[j][N] = mem_rev_link_lo[j]; ++ assign mem_mesh_lo[j][N2-1] = mem_fwd_link_lo[j]; ++ assign mem_mesh_lo[j][S2] = mem_rev_link_lo[j]; + +- assign mem_fwd_link_li[j] = mem_mesh_li[j][N]; +- assign mem_rev_link_li[j] = mem_mesh_li[j][S]; ++ assign mem_fwd_link_li[j] = mem_mesh_li[j][S2]; ++ assign mem_rev_link_li[j] = mem_mesh_li[j][N2-1]; + end +- assign mem_ver_link_li[N] = mem_fwd_link_i; ++ assign mem_ver_link_li[S2] = mem_fwd_link_i; + bsg_mesh_stitch + #(.width_p($bits(bp_mem_ready_and_link_s)) + ,.x_max_p(mc_x_dim_p) +@@ -189,7 +196,7 @@ module bp_mem_complex + ,.ver_i(mem_ver_link_li) + ,.ver_o(mem_ver_link_lo) + ); +- assign mem_rev_link_o = mem_ver_link_lo[N]; ++ assign mem_rev_link_o = mem_ver_link_lo[S2]; + end + else + begin : stub +@@ -197,12 +204,12 @@ module bp_mem_complex + assign coh_cmd_link_o = '0; + assign coh_resp_link_o = '0; + +- assign mem_ver_link_lo[S] = mem_fwd_link_i; +- assign mem_rev_link_o = mem_ver_link_li[S]; ++ assign mem_ver_link_lo[N2-1] = mem_fwd_link_i; ++ assign mem_rev_link_o = mem_ver_link_li[N2-1]; + end + +- assign mem_dma_link_o = mem_ver_link_lo[S]; +- assign mem_ver_link_li[S] = mem_dma_link_i; ++ assign mem_dma_link_o = mem_ver_link_lo[N2-1]; ++ assign mem_ver_link_li[N2-1] = mem_dma_link_i; + + endmodule + +diff --git a/bp_top/src/v/bp_multicore.sv b/bp_top/src/v/bp_multicore.sv +index e455bf7f..bf12ffda 100644 +--- a/bp_top/src/v/bp_multicore.sv ++++ b/bp_top/src/v/bp_multicore.sv +@@ -21,6 +21,12 @@ module bp_multicore + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) + , localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p) + , localparam io_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(io_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ + ) + (input core_clk_i + , input rt_clk_i +@@ -38,11 +44,11 @@ module bp_multicore + , input [io_noc_did_width_p-1:0] my_did_i + , input [io_noc_did_width_p-1:0] host_did_i + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_fwd_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_fwd_link_o + +- , input [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_i +- , output [E:W][io_noc_ral_link_width_lp-1:0] io_rev_link_o ++ , input [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_i ++ , output [E2:W2][io_noc_ral_link_width_lp-1:0] io_rev_link_o + + , output [mc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_dma_link_o + , input [mc_x_dim_p-1:0][mem_noc_ral_link_width_lp-1:0] mem_dma_link_i +@@ -53,28 +59,28 @@ module bp_multicore + `declare_bsg_ready_and_link_sif_s(io_noc_flit_width_p, bp_io_ready_and_link_s); + `declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bp_mem_ready_and_link_s); + +- bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_req_hor_link_li, coh_req_hor_link_lo; +- bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_cmd_hor_link_li, coh_cmd_hor_link_lo; +- bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_fill_hor_link_li, coh_fill_hor_link_lo; +- bp_coh_ready_and_link_s [E:W][cc_y_dim_p-1:0] coh_resp_hor_link_li, coh_resp_hor_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cc_y_dim_p-1:0] coh_req_hor_link_li, coh_req_hor_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cc_y_dim_p-1:0] coh_cmd_hor_link_li, coh_cmd_hor_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cc_y_dim_p-1:0] coh_fill_hor_link_li, coh_fill_hor_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][cc_y_dim_p-1:0] coh_resp_hor_link_li, coh_resp_hor_link_lo; + +- bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_req_ver_link_li, coh_req_ver_link_lo; +- bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_cmd_ver_link_li, coh_cmd_ver_link_lo; +- bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_fill_ver_link_li, coh_fill_ver_link_lo; +- bp_coh_ready_and_link_s [S:N][cc_x_dim_p-1:0] coh_resp_ver_link_li, coh_resp_ver_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][cc_x_dim_p-1:0] coh_req_ver_link_li, coh_req_ver_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][cc_x_dim_p-1:0] coh_cmd_ver_link_li, coh_cmd_ver_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][cc_x_dim_p-1:0] coh_fill_ver_link_li, coh_fill_ver_link_lo; ++ bp_coh_ready_and_link_s [N2:S2][cc_x_dim_p-1:0] coh_resp_ver_link_li, coh_resp_ver_link_lo; + +- bp_mem_ready_and_link_s [N:N][cc_x_dim_p-1:0] mem_fwd_ver_link_li, mem_rev_ver_link_lo; +- bp_mem_ready_and_link_s [S:S][cc_x_dim_p-1:0] mem_rev_ver_link_li, mem_fwd_ver_link_lo; ++ bp_mem_ready_and_link_s [cc_x_dim_p-1:0] mem_fwd_ver_link_li, mem_rev_ver_link_lo; ++ bp_mem_ready_and_link_s [cc_x_dim_p-1:0] mem_rev_ver_link_li, mem_fwd_ver_link_lo; + + // IO and SACC complexes only use Req/Cmd networks +- assign coh_resp_ver_link_li[N] = '0; +- assign coh_resp_hor_link_li[W] = '0; +- assign coh_fill_ver_link_li[N] = '0; +- assign coh_fill_hor_link_li[W] = '0; ++ assign coh_resp_ver_link_li[S2] = '0; ++ assign coh_resp_hor_link_li[W2] = '0; ++ assign coh_fill_ver_link_li[S2] = '0; ++ assign coh_fill_hor_link_li[W2] = '0; + // Memory complex does not use Fill network +- assign coh_fill_ver_link_li[S] = '0; ++ assign coh_fill_ver_link_li[N2-1] = '0; + +- assign mem_fwd_ver_link_li[N] = '0; ++ assign mem_fwd_ver_link_li = '0; + bp_core_complex + #(.bp_params_p(bp_params_p)) + cc +@@ -137,11 +143,11 @@ module bp_multicore + ,.my_did_i(my_did_i) + ,.host_did_i(host_did_i) + +- ,.coh_req_link_i(coh_req_ver_link_lo[N]) +- ,.coh_req_link_o(coh_req_ver_link_li[N]) ++ ,.coh_req_link_i(coh_req_ver_link_lo[S2]) ++ ,.coh_req_link_o(coh_req_ver_link_li[S2]) + +- ,.coh_cmd_link_i(coh_cmd_ver_link_lo[N]) +- ,.coh_cmd_link_o(coh_cmd_ver_link_li[N]) ++ ,.coh_cmd_link_i(coh_cmd_ver_link_lo[S2]) ++ ,.coh_cmd_link_o(coh_cmd_ver_link_li[S2]) + + ,.io_fwd_link_i(io_fwd_link_i) + ,.io_fwd_link_o(io_fwd_link_o) +@@ -164,14 +170,14 @@ module bp_multicore + + ,.my_did_i(my_did_i) + +- ,.coh_req_link_i(coh_req_ver_link_lo[S]) +- ,.coh_req_link_o(coh_req_ver_link_li[S]) ++ ,.coh_req_link_i(coh_req_ver_link_lo[N2-1]) ++ ,.coh_req_link_o(/*coh_req_ver_link_li[N2-1]*/) + +- ,.coh_cmd_link_i(coh_cmd_ver_link_lo[S]) +- ,.coh_cmd_link_o(coh_cmd_ver_link_li[S]) ++ ,.coh_cmd_link_i(coh_cmd_ver_link_lo[N2-1]) ++ ,.coh_cmd_link_o(/*coh_cmd_ver_link_li[N2-1]*/) + +- ,.coh_resp_link_i(coh_resp_ver_link_lo[S]) +- ,.coh_resp_link_o(coh_resp_ver_link_li[S]) ++ ,.coh_resp_link_i(coh_resp_ver_link_lo[N2-1]) ++ ,.coh_resp_link_o(/*coh_resp_ver_link_li[N2-1]*/) + + ,.mem_fwd_link_i(mem_fwd_ver_link_lo) + ,.mem_rev_link_o(mem_rev_ver_link_li) +@@ -189,17 +195,17 @@ module bp_multicore + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + +- ,.coh_req_link_i(coh_req_hor_link_lo[E]) +- ,.coh_req_link_o(coh_req_hor_link_li[E]) ++ ,.coh_req_link_i(coh_req_hor_link_lo[E2-1]) ++ ,.coh_req_link_o(/*coh_req_hor_link_li[E2-1]*/) + +- ,.coh_cmd_link_i(coh_cmd_hor_link_lo[E]) +- ,.coh_cmd_link_o(coh_cmd_hor_link_li[E]) ++ ,.coh_cmd_link_i(coh_cmd_hor_link_lo[E2-1]) ++ ,.coh_cmd_link_o(/*coh_cmd_hor_link_li[E2-1]*/) + +- ,.coh_fill_link_i(coh_fill_hor_link_lo[E]) +- ,.coh_fill_link_o(coh_fill_hor_link_li[E]) ++ ,.coh_fill_link_i(coh_fill_hor_link_lo[E2-1]) ++ ,.coh_fill_link_o(/*coh_fill_hor_link_li[E2-1]*/) + +- ,.coh_resp_link_i(coh_resp_hor_link_lo[E]) +- ,.coh_resp_link_o(coh_resp_hor_link_li[E]) ++ ,.coh_resp_link_i(coh_resp_hor_link_lo[E2-1]) ++ ,.coh_resp_link_o(/*coh_resp_hor_link_li[E2-1]*/) + ); + + bp_sacc_complex +@@ -211,11 +217,11 @@ module bp_multicore + ,.coh_clk_i(coh_clk_i) + ,.coh_reset_i(coh_reset_i) + +- ,.coh_req_link_i(coh_req_hor_link_lo[W]) +- ,.coh_req_link_o(coh_req_hor_link_li[W]) ++ ,.coh_req_link_i(coh_req_hor_link_lo[W2]) ++ ,.coh_req_link_o(coh_req_hor_link_li[W2]) + +- ,.coh_cmd_link_i(coh_cmd_hor_link_lo[W]) +- ,.coh_cmd_link_o(coh_cmd_hor_link_li[W]) ++ ,.coh_cmd_link_i(coh_cmd_hor_link_lo[W2]) ++ ,.coh_cmd_link_o(coh_cmd_hor_link_li[W2]) + ); + + endmodule +diff --git a/bp_top/src/v/bp_sacc_complex.sv b/bp_top/src/v/bp_sacc_complex.sv +index 98e15dbc..8887b516 100644 +--- a/bp_top/src/v/bp_sacc_complex.sv ++++ b/bp_top/src/v/bp_sacc_complex.sv +@@ -12,6 +12,13 @@ module bp_sacc_complex + `declare_bp_proc_params(bp_params_p) + + , localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p) ++ //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; ++ // recalculate assuming W = 0 and S = 0 ++ , parameter logic [2:0] W2 = 0 /*W-W*/ ++ , parameter logic [2:0] E2 = E-W ++ , parameter logic [2:0] S2 = 0 /*S-S*/ ++ , parameter logic [2:0] N2 = S-N /*S is larger*/ ++ , parameter logic [2:0] SW2 = S-W /*S is larger*/ + ) + (input core_clk_i + , input core_reset_i +@@ -29,13 +36,13 @@ module bp_sacc_complex + + `declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s); + +- bp_coh_ready_and_link_s [sac_y_dim_p-1:0][S:W] lce_req_link_li, lce_req_link_lo; +- bp_coh_ready_and_link_s [E:W][sac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_req_ver_link_li, lce_req_ver_link_lo; ++ bp_coh_ready_and_link_s [sac_y_dim_p-1:0][SW2:0] lce_req_link_li, lce_req_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][sac_y_dim_p-1:0] lce_req_hor_link_li, lce_req_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_req_ver_link_li, lce_req_ver_link_lo; + +- bp_coh_ready_and_link_s [sac_y_dim_p-1:0][S:W] lce_cmd_link_li, lce_cmd_link_lo; +- bp_coh_ready_and_link_s [E:W][sac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; +- bp_coh_ready_and_link_s [S:N] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; ++ bp_coh_ready_and_link_s [sac_y_dim_p-1:0][SW2:0] lce_cmd_link_li, lce_cmd_link_lo; ++ bp_coh_ready_and_link_s [E2:W2][sac_y_dim_p-1:0] lce_cmd_hor_link_li, lce_cmd_hor_link_lo; ++ bp_coh_ready_and_link_s [N2:S2] lce_cmd_ver_link_li, lce_cmd_ver_link_lo; + + + for (genvar j=0; j < sac_y_dim_p; j++) +@@ -74,8 +81,8 @@ module bp_sacc_complex + if (sac_x_dim_p > 0) + begin : sac_stitch + assign lce_req_ver_link_li = '0; +- assign lce_req_hor_link_li[W] = '0; +- assign lce_req_hor_link_li[E] = coh_req_link_i; ++ assign lce_req_hor_link_li[W2] = '0; ++ assign lce_req_hor_link_li[E2] = coh_req_link_i; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(sac_x_dim_p) +@@ -90,11 +97,11 @@ module bp_sacc_complex + ,.ver_i(lce_req_ver_link_li) + ,.ver_o(lce_req_ver_link_lo) + ); +- assign coh_req_link_o = lce_req_hor_link_lo[E]; ++ assign coh_req_link_o = lce_req_hor_link_lo[E2]; + + assign lce_cmd_ver_link_li = '0; +- assign lce_cmd_hor_link_li[W] = '0; +- assign lce_cmd_hor_link_li[E] = coh_cmd_link_i; ++ assign lce_cmd_hor_link_li[W2] = '0; ++ assign lce_cmd_hor_link_li[E2] = coh_cmd_link_i; + bsg_mesh_stitch + #(.width_p(coh_noc_ral_link_width_lp) + ,.x_max_p(sac_x_dim_p) +@@ -109,7 +116,7 @@ module bp_sacc_complex + ,.ver_i(lce_cmd_ver_link_li) + ,.ver_o(lce_cmd_ver_link_lo) + ); +- assign coh_cmd_link_o = lce_cmd_hor_link_lo[E]; ++ assign coh_cmd_link_o = lce_cmd_hor_link_lo[E2]; + end + else + begin : stub +-- +2.39.0 +